{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:18:04Z","timestamp":1740133084667,"version":"3.37.3"},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000780","name":"European Commission","doi-asserted-by":"publisher","award":["H2020-687628"],"award-info":[{"award-number":["H2020-687628"]}],"id":[{"id":"10.13039\/501100000780","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000271","name":"STFC","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000271","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2017,9,1]]},"DOI":"10.1109\/tpds.2017.2686389","type":"journal-article","created":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T04:12:11Z","timestamp":1490242331000},"page":"2581-2594","source":"Crossref","is-referenced-by-count":6,"title":["Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon\/Xeon Phi Node"],"prefix":"10.1109","volume":"28","author":[{"given":"George","family":"Chatzikonstantis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitrios","family":"Rodopoulos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christos","family":"Strydis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris I.","family":"De Zeeuw","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitrios","family":"Soudris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Efficient Software Development: 4 What&#x2019;s New in Intel Parallel Studio XE 2013 Service Pack","year":"2013","author":"lubin","key":"ref39"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2009.7478342"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/S0166-2236(98)01310-1"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2016.05.015"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654124"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2009.24"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/CSNT.2015.216"},{"key":"ref36","volume":"2","author":"press","year":"1996","journal-title":"Numerical Recipes in C"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1038\/nrn3011"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pcbi.1002814"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2015.7280424"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.3389\/fninf.2014.00078"},{"key":"ref29","article-title":"Implementation of hardware model for spiking neural network","author":"choi","year":"2015","journal-title":"Proc Int Conf ICAOR"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0071"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470899"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1162\/089976603762552915"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-7320-6_147-1"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1152\/jn.00686.2005"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2004.832719"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.820440"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.3389\/fncom.2011.00049"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2014.6893235"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.04.009"},{"key":"ref51","article-title":"Reconfigurable memory controller with programmable pattern support","author":"hussain","year":"2011","journal-title":"Proc HiPEAC Workshop on Reconfigurable Computing"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"year":"2013","key":"ref11","article-title":"CUDA C Programming Guide"},{"year":"0","key":"ref40"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1002\/cne.901550105"},{"year":"0","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.6.1179"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1162\/NECO_a_00876"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.7554\/eLife.18566"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5536970"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10827-007-0038-6"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008916026143"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-6675-8_258"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"455","DOI":"10.1002\/jcc.21334","article-title":"AutoDock Vina: Improving the speed and accuracy of docking with a new scoring function, efficient optimization, and multithreading","volume":"31","author":"trott","year":"2010","journal-title":"J Comp Chemistry"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1098\/rspb.1952.0054"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2903150.2903477"},{"journal-title":"Intel Xeon Phi Coprocessor High-performance Programming","year":"2013","author":"jeffers","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2568088.2576799"},{"key":"ref49","first-page":"4","article-title":"Secrets of the glasgow haskell compiler inliner","volume":"12","author":"jones","year":"2002","journal-title":"J Functional Program"},{"journal-title":"MPI The Complete Reference - The MPI Core","year":"1998","author":"snir","key":"ref9"},{"key":"ref46","first-page":"1085","article-title":"Exploring simd for molecular dynamics, using intel xeon processors and intel xeon phi coprocessors","author":"pennycook","year":"2013","journal-title":"Proc Int Symp Parallel Distrib Process"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/j.newast.2011.07.001"},{"key":"ref48","article-title":"Best practice guide Intel Xeon phi v1.","volume":"31","author":"barth","year":"2013","journal-title":"LRZ Germany March"},{"article-title":"A guide to vectorization with intel C++ compilers","year":"2012","author":"deilmann","key":"ref47"},{"year":"0","key":"ref42"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2005.03.010"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/40.865866"},{"key":"ref43","article-title":"Introduction to intel advanced vector extensions","author":"lomont","year":"2011","journal-title":"Intel White Paper"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8003561\/07884986.pdf?arnumber=7884986","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T05:31:03Z","timestamp":1719120663000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7884986\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9,1]]},"references-count":51,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2017.2686389","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2017,9,1]]}}}