{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:42:13Z","timestamp":1761896533603,"version":"3.37.3"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2017,10,1]],"date-time":"2017-10-01T00:00:00Z","timestamp":1506816000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea (NRF)","doi-asserted-by":"publisher","award":["NRF-2011-220-D00098","2015-R1D1A1A01059711"],"award-info":[{"award-number":["NRF-2011-220-D00098","2015-R1D1A1A01059711"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2017,10,1]]},"DOI":"10.1109\/tpds.2017.2689010","type":"journal-article","created":{"date-parts":[[2017,3,31]],"date-time":"2017-03-31T02:45:10Z","timestamp":1490928310000},"page":"2896-2910","source":"Crossref","is-referenced-by-count":25,"title":["NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors"],"prefix":"10.1109","volume":"28","author":[{"given":"Ju-Hee","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gi-Ho","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456923"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555760"},{"key":"ref31","first-page":"234","article-title":"i 2 WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations","author":"wang","year":"2013","journal-title":"Proc Int Symp High-Perform Comput Arch"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1529282.1529722"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086732"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.2"},{"key":"ref10","first-page":"1092","article-title":"Prediction table based management policy for STT-RAM and sram hybrid cache","author":"quan","year":"2012","journal-title":"Proc 7th Int Conf Comput Convergence Tech"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2013.6629298"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2361150"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.40"},{"article-title":"MacSim: A CPU-GPU heterogeneous simulation framework user guide","year":"2012","author":"kim","key":"ref17"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"SPEC CPU2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.28"},{"key":"ref28","first-page":"164","article-title":"Balancing thoughput and fairness in SMT processors","author":"luo","year":"2001","journal-title":"Proc Int Symp Perform Anal Syst Softw"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ESTIMedia.2011.6088521"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/356989.357011"},{"key":"ref3","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"0","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782836"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1023\/B:SUPE.0000014800.27383.8f"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.348620"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2019608.2019614"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.35.1516"},{"journal-title":"Advances in Non-volatile Memory and Storage Technology","year":"2014","author":"nishi","key":"ref1"},{"journal-title":"Text Book of Correlations and Regression","year":"2005","author":"sharma","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744909"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2015.7"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742958"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/46\/7\/074001"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.2200\/S00273ED1V01Y201006CAC010"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8030254\/07889038.pdf?arnumber=7889038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:55Z","timestamp":1642003495000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7889038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,1]]},"references-count":38,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2017.2689010","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2017,10,1]]}}}