{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:18:05Z","timestamp":1740133085995,"version":"3.37.3"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea (NRF)","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003621","name":"MSIP","doi-asserted-by":"publisher","award":["NRF-2015R1A2A2A01008281"],"award-info":[{"award-number":["NRF-2015R1A2A2A01008281"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]},{"name":"GPU"},{"name":"IEEE International Symposium on Performance Analysis of Systems and Software","award":["ISPASS 2015"],"award-info":[{"award-number":["ISPASS 2015"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2017,11,1]]},"DOI":"10.1109\/tpds.2017.2704080","type":"journal-article","created":{"date-parts":[[2017,5,12]],"date-time":"2017-05-12T17:46:23Z","timestamp":1494611183000},"page":"3142-3156","source":"Crossref","is-referenced-by-count":4,"title":["Dynamic Resizing on Active Warps Scheduler to Hide Operation Stalls on GPUs"],"prefix":"10.1109","volume":"28","author":[{"given":"Myung Kuk","family":"Yoon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yunho","family":"Oh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seung Hun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sangpil","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deokho","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5390-6445","authenticated-orcid":false,"given":"Won Woo","family":"Ro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485964"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2015.7095804"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056023"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628107"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540718"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446079"},{"article-title":"Parboil: A revised benchmark suite for\n scientific and commercial throughput computing","year":"2012","author":"stratton","key":"ref37"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1735688.1735702"},{"year":"2014","key":"ref35","article-title":"NVIDIA CUDA SDK Code Samples"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815992"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2008.05.014"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485951"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751234"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446062"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.59"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2166879.2166882"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835938"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056031"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540747"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref28","first-page":"157","article-title":"Neither more nor less: Optimizing\n thread-level parallelism for GPGPUs","author":"kayiran","year":"2013","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2008.05.014"},{"year":"2015","key":"ref3","article-title":"NVIDIA’s Next Generation CUDA Compute Architecture: Kepler GK 110"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370858"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451158"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749714"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835939"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454152"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.24"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835939"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"year":"2014","key":"ref21","article-title":"Fermi: NVIDIAs next generation CUDA compute architecture"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001158"},{"year":"2015","key":"ref24","article-title":"White paper: AMD graphics cores next (GCN) architecture"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"year":"2016","key":"ref23","article-title":"Whitepaper: NVIDIA GeForce GTX980"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628105"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815998"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540719"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237005"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8063268\/07927466.pdf?arnumber=7927466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:39:22Z","timestamp":1641987562000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927466\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11,1]]},"references-count":45,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2017.2704080","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2017,11,1]]}}}