{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:07:27Z","timestamp":1780445247235,"version":"3.54.1"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/USG.html"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/USG.html"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1302557"],"award-info":[{"award-number":["1302557"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1213052"],"award-info":[{"award-number":["1213052"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1439021"],"award-info":[{"award-number":["1439021"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1302225"],"award-info":[{"award-number":["1302225"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1629129"],"award-info":[{"award-number":["1629129"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1526750"],"award-info":[{"award-number":["1526750"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1629915"],"award-info":[{"award-number":["1629915"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2017,11,1]]},"DOI":"10.1109\/tpds.2017.2705125","type":"journal-article","created":{"date-parts":[[2017,5,17]],"date-time":"2017-05-17T18:24:30Z","timestamp":1495045470000},"page":"3188-3200","source":"Crossref","is-referenced-by-count":13,"title":["HL-PCM: MLC PCM Main Memory with Accelerated Read"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1213-7349","authenticated-orcid":false,"given":"Mohammad","family":"Arjomand","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amin","family":"Jadidi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mahmut T.","family":"Kandemir","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Anand","family":"Sivasubramaniam","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335248"},{"key":"ref33","first-page":"210","article-title":"Efficient discovery of regular stride patterns in irregular programs and its use\n in compiler prefetching","author":"wu","year":"2010","journal-title":"Proc Conf Programming Language Design and Implementation"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2002.1106017"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155672"},{"key":"ref30","first-page":"63","article-title":"Feedback directed prefetching: Improving\n the performance and bandwidth-efficiency of hardware prefetchers","author":"srinath","year":"2008","journal-title":"Proc Int Symp High Performance Comput Archit"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360134"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736045"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2009.61"},{"key":"ref34","article-title":"Accurate, timely data prefetching for regular stream, linked data structure, and\n correlated miss pattern","author":"liu","year":"2010"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056042"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765953"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.11"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665724"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref15","first-page":"455","article-title":"Write strategies for 2 and 4-bit multi-level phase-change\n memory","author":"nirschl et","year":"2014","journal-title":"Proc Int Electron Devices Meet"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.71"},{"key":"ref18","year":"2010","journal-title":"Micron movile LPDDR2 part MT42L128M16D1"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749742"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000081"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref27","first-page":"18:1","article-title":"Memory performance attacks: Denial of memory service in multi-core systems","author":"moscibroda","year":"2007","journal-title":"Proc 16th USENIX Security Symp USENIX Security Symp"},{"key":"ref3","first-page":"339","article-title":"Challenges for the DRAM cell scaling to 40 nm","author":"mueller et","year":"2005","journal-title":"Proc Int Electron Devices Meet"},{"key":"ref6","article-title":"Gb: x4, x8, x16 DDR3 SDRAM Features","year":"2006"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771791"},{"key":"ref5","first-page":"46","article-title":"A 20 nm 1.8 V 8 Gb PRAM with 40 MB\/s program bandwidth","author":"choi et","year":"2012","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref8","first-page":"289","article-title":"Meeting midway: Improving CMP performance with memory-side prefetching","author":"yedlapalli","year":"2013","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482082"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1713254.1713276"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853228"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815967"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815981"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763155"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref24","article-title":"PARSEC 2.0: A new benchmark suite for chip-multiprocessors","author":"bienia","year":"2009","journal-title":"Proc Workshop Model Benchmarking Simul"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995911"},{"key":"ref44","article-title":"Critical words cache memory: Exploiting criticality within primary\n cache miss streams","author":"gieske","year":"2008"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1063\/1.1598272"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241625"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/71\/8063268\/7930492-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8063268\/07930492.pdf?arnumber=7930492","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:48:42Z","timestamp":1649443722000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7930492\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11,1]]},"references-count":44,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2017.2705125","relation":{},"ISSN":["1045-9219"],"issn-type":[{"value":"1045-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2017,11,1]]}}}