{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:25:17Z","timestamp":1747895117928,"version":"3.37.3"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2017,11,1]],"date-time":"2017-11-01T00:00:00Z","timestamp":1509494400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2017,11,1]]},"DOI":"10.1109\/tpds.2017.2719679","type":"journal-article","created":{"date-parts":[[2017,6,26]],"date-time":"2017-06-26T18:07:44Z","timestamp":1498500464000},"page":"3313-3327","source":"Crossref","is-referenced-by-count":3,"title":["TC-Release++: An Efficient Timestamp-Based Coherence Protocol for Many-Core Architectures"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7479-9263","authenticated-orcid":false,"given":"Yuan","family":"Yao","sequence":"first","affiliation":[]},{"given":"Wenzhi","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Tulika","family":"Mitra","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5252-0831","authenticated-orcid":false,"given":"Yang","family":"Xiang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750405"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370853"},{"key":"ref33","first-page":"240","article-title":"An incessantly coherent cache scheme for shared memory multithreaded systems","author":"nandy","year":"0","journal-title":"Proc Int Workshop Parallel Process"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1996.538566"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/71.113080"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024406"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/ISCA.1995.524548","article-title":"Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors","author":"lebeck","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.37"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835927"},{"key":"ref34","first-page":"261","article-title":"Tardis 2.0: Optimized time traveling coherence for relaxed consistency models","author":"yu","year":"2016","journal-title":"Proc Int Conf Parallel Archit Compil"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.239"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.21"},{"year":"1999","key":"ref11","article-title":"Alpha 21264 microprocessor hardware reference manual"},{"year":"2002","key":"ref12","article-title":"Formal specification of intel itanium processor family memory ordering"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835930"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134502"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-61474-5_86"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44798-9_17"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 Simulator","volume":"39","author":"binkert","year":"2011","journal-title":"Comput Archit News"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1123001"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694356"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749726"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522351"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168950"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081367"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134503"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434074"},{"key":"ref5","first-page":"227","article-title":"Tardis: Time traveling coherence algorithm for distributed shared memory","author":"yu","year":"2015","journal-title":"Proc Int Conf Parallel Archit Compil"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1992.753300"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01733-9","author":"sorin","year":"2011","journal-title":"A Primer on Memory Consistency and Cache Coherence"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545239"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2209249.2209269"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783729"},{"key":"ref22","first-page":"137","article-title":"Model checking of consensus algorithms","author":"tsuchiya","year":"2007","journal-title":"Proc 26th IEEE Int Symp Reliable Distrib Syst"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44577-3_12"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"ref24","first-page":"100","article-title":"Verifying security protocols with timestamps via translation to timed automata","author":"jakubowska","year":"2005","journal-title":"Proc Int Workshop Concurrency Specification Programming"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451119"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45251-6_7"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.155"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8063268\/07959101.pdf?arnumber=7959101","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,25]],"date-time":"2024-06-25T00:16:26Z","timestamp":1719274586000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7959101\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11,1]]},"references-count":43,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2017.2719679","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2017,11,1]]}}}