{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:19:18Z","timestamp":1774365558811,"version":"3.50.1"},"reference-count":64,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61774094"],"award-info":[{"award-number":["61774094"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"China Major S&T Project","award":["2018ZX01031101-002"],"award-info":[{"award-number":["2018ZX01031101-002"]}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1718158\/1725447\/1719160"],"award-info":[{"award-number":["1718158\/1725447\/1719160"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2019,1,1]]},"DOI":"10.1109\/tpds.2018.2858230","type":"journal-article","created":{"date-parts":[[2018,7,20]],"date-time":"2018-07-20T18:40:07Z","timestamp":1532112007000},"page":"146-160","source":"Crossref","is-referenced-by-count":15,"title":["Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2309-572X","authenticated-orcid":false,"given":"Shouyi","family":"Yin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shibin","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinhan","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Ouyang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2228-8829","authenticated-orcid":false,"given":"Fengbin","family":"Tu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7548-4116","authenticated-orcid":false,"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jishen","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cong","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuangcheng","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2093-1788","authenticated-orcid":false,"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5117-7920","authenticated-orcid":false,"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref38","first-page":"1393","article-title":"Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array","author":"atul rahman","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418003"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001165"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897995"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001179"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001138"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418008"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055293"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055294"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783723"},{"key":"ref62","year":"2010","journal-title":"DDR3 SDRAM Specification JESD79–3E"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837308"},{"key":"ref63","first-page":"1","article-title":"RAIDR: Retention-aware intelligent DRAM refresh","author":"liu","year":"2012","journal-title":"Proc 39th Annu Int Symp Comput Archit"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref64","first-page":"432","article-title":"25.2 a 1.2 v 8 gb 8-channel 128 gb\/s high-bandwidth memory (HBM) stacked dram\n with effective microbump i\/o test methods using 29 nm process and tsv","author":"lee","year":"2014","journal-title":"Proc IEEE Int Solid-State Circuits Conf Digest Tech Papers"},{"key":"ref27","first-page":"683","article-title":"A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters","author":"conti","year":"2015","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750389"},{"key":"ref2","article-title":"Pathnet: Evolution channels gradient descent in\n super neural networks","author":"fernando","year":"2017","journal-title":"arXiv preprint arXiv 1701 07717"},{"key":"ref1","first-page":"1097","article-title":"Imagenet\n classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref20","article-title":"Temperature aware\n energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia mpsocs","author":"das","year":"2014","journal-title":"Proc Conf Des Autom Test Eur"},{"key":"ref22","first-page":"33","article-title":"Cacti-3dd: Architecture-level modeling for 3d die-stacked dram main memory","author":"chen","year":"2012","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref21","article-title":"Meet TPU 3.0: Google teases world with latest math coprocessor for\n AI","author":"thomson","year":"2018"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"ref23","article-title":"Hotspot\n 6.0: Validation, acceleration and extension","author":"zhang","year":"2015","journal-title":"University of Virginia Charlottesville VA USA Tech Rep CS-2015-04"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657019"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815993"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICWSI.1993.255272"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783725"},{"key":"ref57","article-title":"Wave Computing's Native Dataflow Technology","author":"computing","year":"0"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147160"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"ref53","article-title":"JEDEC 3D ICs Interface","year":"2016"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047127"},{"key":"ref10","article-title":"Very deep convolutional networks for large-scale image recognition","volume":"abs 1409 1556","author":"simonyan","year":"2015","journal-title":"Proc Int Conf Learn Representations"},{"key":"ref11","article-title":"One\n model to learn them all","author":"kaiser","year":"2017","journal-title":"arXiv preprint arXiv 1706 05137"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001178"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.2200\/S00644ED1V01Y201505CAC031"},{"key":"ref16","first-page":"1","article-title":"Amd's next generation gpu and memory architecture - hot chips","year":"2015","journal-title":"Proc Hot Chips Symp"},{"key":"ref17","article-title":"Pascal gpu architecture","year":"0"},{"key":"ref18","first-page":"1","article-title":"Knights landing (knl): 2nd generation intel xeon phi processor","year":"2015","journal-title":"Proc Hot Chips"},{"key":"ref19","article-title":"Intel Nervana Neural Network Processor","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298878"},{"key":"ref6","article-title":"Deep compression:\n Compressing deep neural network with pruning, trained quantization and huffman coding","author":"han","year":"2016","journal-title":"International Conference on Learning Representations"},{"key":"ref5","first-page":"1135","article-title":"Learning both weights and connections for efficient\n neural networks","author":"han","year":"2015","journal-title":"Neural Inf Process Syst"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1145\/2644865.2541967","article-title":"Diannao: A small-footprint\n high-throughput accelerator for ubiquitous machine-learning","volume":"49","author":"chen","year":"2014","journal-title":"ACM SIGPLAN Notices"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.37"},{"key":"ref9","article-title":"Caffeine: Towards uniformed representation and acceleration for\n deep convolutional neural networks","author":"chen","year":"2016","journal-title":"Proc Int Conf Comput Aided Des"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577315"},{"key":"ref45","first-page":"1","article-title":"A high\n performance fpga-based accelerator for large-scale convolutional neural networks","author":"li","year":"2016","journal-title":"Proc Int Conf Field Program Logic and Appl"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2016.7482563"},{"key":"ref47","first-page":"513","article-title":"Dlau: A scalable deep learning accelerator unit on fpga","volume":"36","author":"wang","year":"2017","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272559"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW.2014.106"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2009.25"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielaam\/71\/8572813\/8416708-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8572813\/08416708.pdf?arnumber=8416708","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:43:49Z","timestamp":1657745029000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8416708\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1,1]]},"references-count":64,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2018.2858230","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1,1]]}}}