{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:18:33Z","timestamp":1740133113093,"version":"3.37.3"},"reference-count":49,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2019,8,1]],"date-time":"2019-08-01T00:00:00Z","timestamp":1564617600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,8,1]],"date-time":"2019-08-01T00:00:00Z","timestamp":1564617600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,8,1]],"date-time":"2019-08-01T00:00:00Z","timestamp":1564617600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2019,8,1]]},"DOI":"10.1109\/tpds.2019.2896633","type":"journal-article","created":{"date-parts":[[2019,1,31]],"date-time":"2019-01-31T20:09:45Z","timestamp":1548965385000},"page":"1704-1721","source":"Crossref","is-referenced-by-count":5,"title":["Analytical Derivation of Concurrent Reuse Distance Profile for Multi-Threaded Application Running on Chip Multi-Processor"],"prefix":"10.1109","volume":"30","author":[{"given":"Jasmine Madonna","family":"Sabarimuthu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0676-512X","authenticated-orcid":false,"given":"T.G.","family":"Venkatesh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2006.1620793"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2004.1291352"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1109\/TC.2017.2723878","article-title":"Analytical miss rate calculation of L2 cache from the RD profile of L1 cache","volume":"67","author":"madonna","year":"2018","journal-title":"IEEE Trans Comput"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2701370"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.31"},{"article-title":"A composable model for analyzing locality of multi-threaded programs","year":"2009","author":"ding","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451153"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1190215.1190227"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-49956-7_4"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.11"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-014-1460-7"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.58"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.50"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2007.17"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.2200\/S00273ED1V01Y201006CAC010"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1552309.1552310"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1147\/sj.92.0078"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/780822.781159"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11970-5_15"},{"article-title":"Reuse distance analysis","year":"2001","author":"ding","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854286"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470780"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2713778"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/63404.63407"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452069"},{"key":"ref12","article-title":"Footprints in the cache","volume":"11","author":"thiebaut","year":"1996","journal-title":"Performance Modeling for Computer Architects"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377797"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454130"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2465529.2465756"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782836"},{"key":"ref18","first-page":"350","article-title":"Reuse distance as a metric for cache behavior","volume":"14","author":"beyls","year":"2001","journal-title":"Proc IASTED Conf Parallel Distrib Comput Syst"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.141"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"ref5","first-page":"76","article-title":"Cache contention and application performance prediction for multi-core systems","author":"xu","year":"2010","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2127330"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2006.404"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"ref9","first-page":"64","article-title":"and IA-32 architectures software developers manual","volume":"1","author":"intel","year":"0","journal-title":"Volume 3A System Programming Guide"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3018743.3018759"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref48","first-page":"485","article-title":"Analysis of demand paging algorithms","author":"king","year":"1971","journal-title":"Proc IFIP Congr"},{"key":"ref47","first-page":"286","article-title":"On the effectiveness of set associative page mapping and its applications in main memory management","author":"smith","year":"1976","journal-title":"Proc Int Conf Softw Eng"},{"key":"ref42","first-page":"156","article-title":"Coherence communication prediction in shared-memory multiprocessors","author":"kaxiras","year":"2000","journal-title":"Proc Int Symp High-Perform Comput Arch"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854347"},{"article-title":"Benchmarking modern multiprocessors","year":"2011","author":"bienia","key":"ref44"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2015.7095782"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8763865\/08630685.pdf?arnumber=8630685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:42:39Z","timestamp":1657744959000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8630685\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,8,1]]},"references-count":49,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2019.2896633","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"type":"print","value":"1045-9219"},{"type":"electronic","value":"1558-2183"},{"type":"electronic","value":"2161-9883"}],"subject":[],"published":{"date-parts":[[2019,8,1]]}}}