{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:39:03Z","timestamp":1773193143759,"version":"3.50.1"},"reference-count":83,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Key Research and Development Plan of China","award":["2017YFB1001602"],"award-info":[{"award-number":["2017YFB1001602"]}]},{"name":"NSF","award":["61502452"],"award-info":[{"award-number":["61502452"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2019,10,1]]},"DOI":"10.1109\/tpds.2019.2908175","type":"journal-article","created":{"date-parts":[[2019,3,29]],"date-time":"2019-03-29T18:37:54Z","timestamp":1553884674000},"page":"2223-2236","source":"Crossref","is-referenced-by-count":49,"title":["Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4854-7382","authenticated-orcid":false,"given":"Lei","family":"Liu","sequence":"first","affiliation":[]},{"given":"Shengjie","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Lu","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Xinyu","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2208129"},{"key":"ref71","article-title":"DRAFT: Towards O(1) Memory","author":"swift","year":"2017"},{"key":"ref70","first-page":"123","article-title":"Safetynet: Improving the availability of shared memory multiprocessors with global checkpoint\/Recovery","author":"sorin","year":"0","journal-title":"Proc 29th IEEE Ann Int Symp Comput Arch"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039420"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451153"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835960"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-67952-5_5"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"ref78","first-page":"13","article-title":"Adaptive placement and migration policy for an STT-RAM-based hybrid cache","year":"2014","journal-title":"Proc IEEE 20th Int Symp High Perform Comput Archit"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1145\/1519065.1519076"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317810"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.33"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753318"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2451512.2451543"},{"key":"ref36","first-page":"31","article-title":"A NUCA substrate for flexible CMP cache sharing","author":"huh","year":"0","journal-title":"Proc 19th Annual Int' i Conf Supercomputing"},{"key":"ref35","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1145\/2669594.2669599","article-title":"A tool to instrument x86-64 TLB misses","volume":"42","author":"gandhi","year":"0","journal-title":"SIGARCH Comput Archit News"},{"key":"ref34","first-page":"85","article-title":"Page placement in hybrid memory systems","year":"2011","journal-title":"Proc Int Conf Supercomput"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4939-2163-8_6"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173203"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"ref63","article-title":"Linux kernel support to exploit phase change memory","author":"park","year":"0","journal-title":"Proc Linux Symp"},{"key":"ref28","first-page":"211","article-title":"SSDAlloc: Hybrid SSD\/RAM memory management made easy","author":"badam","year":"2011","journal-title":"Proc 8th USENIX Conf Netw Syst Des Implementation"},{"key":"ref64","author":"qureshi","year":"2011","journal-title":"Phase Change Memory From Devices to Systems"},{"key":"ref27","first-page":"273","article-title":"Avoiding TLB shootdowns through self-invalidating TLB entries","author":"awad","year":"2017","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"ref68","first-page":"936","article-title":"An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture","author":"reza salkhordeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1145\/1982185.1982312"},{"key":"ref2","year":"0"},{"key":"ref1","year":"0"},{"key":"ref20","year":"0"},{"key":"ref22","year":"2015"},{"key":"ref21","article-title":"Utility-based hybrid memory management simulator","year":"2017"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2749441"},{"key":"ref23","author":"morgan","year":"2015"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872377"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037706"},{"key":"ref50","doi-asserted-by":"crossref","first-page":"367","DOI":"10.1145\/2370816.2370869","article-title":"A Software Memory Partition Approach for Eliminating Bank-Level Interference in Multicore Systems","author":"lei liu","year":"2012","journal-title":"In International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/2579672"},{"key":"ref59","article-title":"Operating system support for NVM+DRAM Hybrid main memory","author":"mogul","year":"2009","journal-title":"Proceedings of the 12th Conference on Hot Topics in Operating Systems"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.14.0114.0012"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-015-1427-7"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-013-1409-2"},{"key":"ref55","first-page":"1","article-title":"NVM aware MariaDB database system","author":"lindstom","year":"2015","journal-title":"Proc IEEE Non-Volatile Memory Syst Appl Symp"},{"key":"ref54","article-title":"Memory resource optimization method and apparatus","author":"liu","year":"0"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2462813"},{"key":"ref52","first-page":"169","article-title":"Going vertical in memory management: Handling multiplicity by multi-policy","author":"liu","year":"0","journal-title":"Proceeding of the 41st annual international symposium on Computer architecuture"},{"key":"ref10","year":"0"},{"key":"ref11","year":"0"},{"key":"ref40","first-page":"521","article-title":"HeteroOS: OS design for heterogeneous memory management in datacenter","author":"kannan","year":"0","journal-title":"Proc ACM\/IEEE Annu Int Symp Comput Archit"},{"key":"ref12","year":"0"},{"key":"ref13","year":"0"},{"key":"ref14","year":"0"},{"key":"ref15","year":"0"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref16","year":"0"},{"key":"ref81","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1145\/360128.360134","article-title":"A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality","author":"zhang","year":"2000","journal-title":"Proc 33rd Annu ACM\/IEEE Int Symp Microarchitecture"},{"key":"ref17","year":"0"},{"key":"ref18","year":"0"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1145\/2451512.2451547"},{"key":"ref19","year":"0"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694370"},{"key":"ref4","year":"0"},{"key":"ref3","year":"0"},{"key":"ref6","year":"0"},{"key":"ref5","year":"0"},{"key":"ref8","year":"0"},{"key":"ref7","year":"2014"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753305"},{"key":"ref9","year":"0"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTER.2017.130"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.98"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872401"},{"key":"ref47","first-page":"367","article-title":"Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems","author":"lin","year":"0","journal-title":"Proc IEEE 14th Int Symp High Perform Comput Archit"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref43","first-page":"705","article-title":"Coordinated and efficient huge page management with ingens","author":"kwon","year":"0","journal-title":"Proc 11th USENIX Conf Operating Syst Des Implementation"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/8830308\/08676386.pdf?arnumber=8676386","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:14:23Z","timestamp":1657746863000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8676386\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10,1]]},"references-count":83,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2019.2908175","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,10,1]]}}}