{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:31:35Z","timestamp":1780673495832,"version":"3.54.1"},"reference-count":103,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000781","name":"European Research Council","doi-asserted-by":"publisher","award":["678880"],"award-info":[{"award-number":["678880"]}],"id":[{"id":"10.13039\/501100000781","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2021,5,1]]},"DOI":"10.1109\/tpds.2020.3039409","type":"journal-article","created":{"date-parts":[[2020,11,20]],"date-time":"2020-11-20T02:24:27Z","timestamp":1605839067000},"page":"1014-1029","source":"Crossref","is-referenced-by-count":80,"title":["Transformations of High-Level Synthesis Codes for High-Performance Computing"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1500-7411","authenticated-orcid":false,"given":"Johannes","family":"de Fine Licht","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6550-7916","authenticated-orcid":false,"given":"Maciej","family":"Besta","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9736-4745","authenticated-orcid":false,"given":"Simon","family":"Meierhans","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9611-7171","authenticated-orcid":false,"given":"Torsten","family":"Hoefler","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2614981"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174248"},{"key":"ref33","article-title":"Deep learning on FPGAs: Past, present, and future","author":"lacey","year":"2016"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3320060"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2491956.2462176"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2601097.2601174"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950429"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3242897"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref34","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or -1","author":"courbariaux","year":"2016"},{"key":"ref28","author":"taflove","year":"1995","journal-title":"Computational Electrodynamics The Finite-Difference Time-Domain Method"},{"key":"ref27","author":"smith","year":"1985","journal-title":"Numerical Solution of Partial Differential Equations Finite Difference Methods"},{"key":"ref29","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-97035-1","author":"fletcher","year":"1988","journal-title":"Computational Techniques for Fluid Dynamics 2"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228411"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869469"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903392"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/S1571-0661(04)80820-X"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345220"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/197405.197406"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375296"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.51"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/106973.106981"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/109025.109083"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/502949.502897"},{"key":"ref56","article-title":"Enabling impactful DSP designs on FPGAs with hardened floating-point implementation","author":"sinha","year":"2014"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626412500107"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00037"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28365-9_3"},{"key":"ref52","article-title":"Systolic arrays (for VLSI)","author":"kung","year":"1978","journal-title":"Sparse Matrix Proceedings"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753287"},{"key":"ref4","article-title":"Where's the beef? Why FPGAs are so fast","author":"sirowy","year":"2008","journal-title":"Microsoft Research"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653942"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508139"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/540159"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"key":"ref49","article-title":"High-performance dynamic programming on FPGAs with OpenCL","author":"settle","year":"2013","journal-title":"Proc IEEE High Perform Extreme Comput Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2436256.2436271"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375300"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00020"},{"key":"ref48","article-title":"hlslib: Software engineering for hardware design","author":"hoefler","year":"2019"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/567532.567555"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718356"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339257"},{"key":"ref44","article-title":"StencilFlow: Mapping large stencil programs to distributed spatial computing systems","author":"de fine licht","year":"0"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145704"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/3295500.3356201"},{"key":"ref72","author":"aho","year":"1986","journal-title":"Compilers Principles Techniques"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1145\/956641.956647"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380160704"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021698"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021730"},{"key":"ref75","article-title":"Accelerating workloads on FPGAs via OpenCL: A case study with opendwarfs","author":"verma","year":"2016"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/3039902.3039916"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00020"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-18991-2_15"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1145\/321312.321314"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/356683.356686"},{"key":"ref63","article-title":"Optimizing supercompilers for supercomputers","author":"wolfe","year":"1982"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380090307"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/960116.54022"},{"key":"ref66","article-title":"Loop coalescing: A compiler transformation for parallel machines","author":"polychronopoulos","year":"1987"},{"key":"ref67","author":"allen","year":"1971","journal-title":"A catalogue of optimizing transformations"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174264"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1145\/359863.359888"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435273"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26408-0_8"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027087"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2003.1183177"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2016.28"},{"key":"ref103","article-title":"Intel FPGA SDK for OpenCL Pro Edition Best Practices Guide","year":"2020"},{"key":"ref102","article-title":"Programming MPC systems (white paper)","year":"2013"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"ref99","first-page":"427","article-title":"A common backend for hardware acceleration on FPGA","author":"sozzo","year":"2017","journal-title":"Proc IEEE Int Conf Comput Des"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1145\/3107953"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375320"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9096-8"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8_6"},{"key":"ref13","article-title":"Intel HLS Compiler: Fast Design, Coding, and Hardware","author":"sussmann","year":"0"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8_3"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00036"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339221"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293916"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.19"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2016.34"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/Trustcom.2015.634"},{"key":"ref80","article-title":"Graph processing on FPGAs: Taxonomy, survey, challenges","author":"besta","year":"2019"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270297"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1145\/3295500.3356173"},{"key":"ref86","article-title":"Parallel programming for FPGAs","author":"kastner","year":"2018"},{"key":"ref87","first-page":"218","article-title":"Module-per-Object: A human-driven methodology for C++-based high-level synthesis design","author":"da silva","year":"2019","journal-title":"Proc IEEE 27th Annu Int Symp Field-Programmable Custom Comput Mach"},{"key":"ref88","first-page":"1","article-title":"A case for better integration of host and target compilation when using OpenCL for FPGAs","author":"lloyd","year":"2017","journal-title":"Proc 4th Int Workshop FPGAs Softw Programmers"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/9275496\/09264692.pdf?arnumber=9264692","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,17]],"date-time":"2024-08-17T19:25:02Z","timestamp":1723922702000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9264692\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5,1]]},"references-count":103,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2020.3039409","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,5,1]]}}}