{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T15:59:01Z","timestamp":1772207941938,"version":"3.50.1"},"reference-count":84,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Cisco Research Center","award":["CG#1490376"],"award-info":[{"award-number":["CG#1490376"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2021,9,1]]},"DOI":"10.1109\/tpds.2021.3063670","type":"journal-article","created":{"date-parts":[[2021,3,3]],"date-time":"2021-03-03T20:33:16Z","timestamp":1614803596000},"page":"2216-2230","source":"Crossref","is-referenced-by-count":42,"title":["A Survey of System Architectures and Techniques for FPGA Virtualization"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6939-1669","authenticated-orcid":false,"given":"Masudul Hassan","family":"Quraishi","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3248-9301","authenticated-orcid":false,"given":"Erfan Bank","family":"Tavakoli","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6509-8753","authenticated-orcid":false,"given":"Fengbo","family":"Ren","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2014.7032514"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370535"},{"key":"ref71","article-title":"Architecture centric coarse-grained FPGA overlays","author":"jain","year":"2017"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.25"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194644"},{"key":"ref77","article-title":"Vivado design suite partial reconfiguration user guide","year":"0"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2017.2679183"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3154839"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378482"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2012.78"},{"key":"ref78","article-title":"SDAccel development environment","year":"2016"},{"key":"ref79","article-title":"Xilinx isolation design flow","year":"2019"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2499625.2499628"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658997"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577389"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/CLOUD.2016.0013"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-1791-0_25"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393130"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.03.002"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2017.8279796"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.110"},{"key":"ref62","article-title":"Intel&#x00AE; SDK for OpenCL&#x2122; applications","year":"2020"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26408-0_14"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1145\/1165389.945462"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2748393"},{"key":"ref64","article-title":"OpenStack - Open source software for building private and public clouds","year":"2020"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IITA.2009.334"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927507"},{"key":"ref66","article-title":"Virtio-vsock: Zero-configuration host\/guest communication","author":"hajnoczi","year":"2015"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.42"},{"key":"ref67","author":"lindholm","year":"2014","journal-title":"The Java Virtual Machine Specification"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1145\/3339861"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1145\/2038698.2038728"},{"key":"ref2","article-title":"F1 instances: Run custom FPGAs in the AWS cloud","year":"2017"},{"key":"ref1","article-title":"Are FPGAs suitable for edge computing?","author":"biookaghazadeh","year":"2018","journal-title":"Proc USENIX Workshop Hot Topics Edge Comput"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44687-7_37"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124743"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26408-0_16"},{"key":"ref24","article-title":"Virtualizing reconfigurable hardware to provide scalability in cloud architectures","author":"knodel","year":"2017","journal-title":"Proc 10th Int Conf Advances Circuits Electron Micro-Electronics"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00028"},{"key":"ref26","first-page":"107","article-title":"Sharing, protection, and compatibility for reconfigurable fabric with amorphos","author":"khawaja","year":"2018","journal-title":"Proc 13th USENIX Symp Operating Syst Des Implementation"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929187"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2016.21"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2661582"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878966"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00023"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378491"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.2017RCP0004"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/CLOUD.2018.00122"},{"key":"ref54","first-page":"242","article-title":"FPGA virtualization in cloud-based infrastructures over virtio","author":"mbongue","year":"2018","journal-title":"Proc IEEE 36th Int Conf Comput Des"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2017.8344606"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056807"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2009.7478342"},{"key":"ref11","article-title":"Halo 1.0: A hardware-agnostic accelerator orchestration framework for enabling hardware-agnostic programming with true performance portability for heterogeneous HPC","author":"riera","year":"2020"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2009.2028039"},{"key":"ref12","first-page":"63","article-title":"Virtualization of hardware - introduction and survey","author":"plessl","year":"2004","journal-title":"Proc Int Conf Eng Reconfigurable Syst Algorithms"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00031"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.3390\/fi12040064"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1155\/2019\/8085461"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2018.00049"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2014.7082768"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2919644"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2012.136"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HiPC.2011.6152718"},{"key":"ref83","article-title":"Accelerating DNNs with Xilinx alveo accelerator cards","year":"0"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-64359-1_665"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942094"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008155020711"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9660-2"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1002\/9780470713785"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2947639"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927483"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/CloudCom.2015.60"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554785"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597929"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145728"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/UIC-ATC-ScalCom-CBDCom-IoP.2015.199"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.108"},{"key":"ref42","article-title":"Firm-core virtual FPGA for just-in-time FPGA compilation","author":"lysecky","year":"2005","journal-title":"Proc ACM\/SIGDA 12th Int Symp Field Programmable Gate Arrays"},{"key":"ref41","first-page":"90","article-title":"General methodologies to virtualize FPGAs in hw\/sw systems","author":"fornaciari","year":"1998","journal-title":"Proc Midwest Symp Circuits Syst"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.54"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/HPRCTA.2008.4745683"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/9380848\/09369140.pdf?arnumber=9369140","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:26Z","timestamp":1652194226000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9369140\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,1]]},"references-count":84,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2021.3063670","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,9,1]]}}}