{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:18:15Z","timestamp":1740133095491,"version":"3.37.3"},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Spanish Government","award":["SEV2015-0493","BES-2017-080635"],"award-info":[{"award-number":["SEV2015-0493","BES-2017-080635"]}]},{"DOI":"10.13039\/501100004837","name":"Ministerio de Ciencia e Innovaci\u00f3n","doi-asserted-by":"publisher","award":["PID2019-107255GB-C21\/AEI\/10.13039\/501100011033","RTI2018-098156-B-C53"],"award-info":[{"award-number":["PID2019-107255GB-C21\/AEI\/10.13039\/501100011033","RTI2018-098156-B-C53"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ECHO and RoMoL ERC","award":["819134","321253"],"award-info":[{"award-number":["819134","321253"]}]},{"name":"European HiPEAC Network","award":["EU-FP7-610402","EU-H2020-779877"],"award-info":[{"award-number":["EU-FP7-610402","EU-H2020-779877"]}]},{"name":"Spanish Ministry of Economy, Industry and Competitiveness","award":["RYC-2016-21104","RYC-2017-23269","RYC-2018-025200-I"],"award-info":[{"award-number":["RYC-2016-21104","RYC-2017-23269","RYC-2018-025200-I"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2022,4,1]]},"DOI":"10.1109\/tpds.2021.3091015","type":"journal-article","created":{"date-parts":[[2021,6,22]],"date-time":"2021-06-22T19:34:05Z","timestamp":1624390445000},"page":"779-791","source":"Crossref","is-referenced-by-count":0,"title":["Compiler-Assisted Compaction\/Restoration of SIMD Instructions"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3731-9301","authenticated-orcid":false,"given":"Juan M.","family":"Cebrian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thibaud","family":"Balem","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9435-3234","authenticated-orcid":false,"given":"Adrian","family":"Barredo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Casas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9848-8758","authenticated-orcid":false,"given":"Miquel","family":"Moreto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5757-1064","authenticated-orcid":false,"given":"Alberto","family":"Ros","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8642-2447","authenticated-orcid":false,"given":"Alexandra","family":"Jimborean","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1137\/17M1115873"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.and.EUC.2013.80"},{"article-title":"CACTI 6.0: A Tool to Understand Large Caches","year":"0","author":"muralimanohar","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056064"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"article-title":"Normally distributed random number generator benchmark","year":"2015","author":"yip","key":"ref37"},{"article-title":"A 2D N-body solver, with OpenMP, MPI and AVX","year":"2015","author":"davies","key":"ref36"},{"year":"0","key":"ref35","article-title":"Genus synthesis solution"},{"year":"0","key":"ref34","article-title":"Precision RTL plus"},{"year":"0","key":"ref10","article-title":"ARM NEON Technology"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1137\/16M1062454"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.35"},{"year":"0","key":"ref12","article-title":"3DNow! technology manual."},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477467"},{"key":"ref14","article-title":"Introduction of Fujitsu's HPC processor for the Post-K computer","author":"yoshida","year":"2016","journal-title":"Keynote Proc Hot Chips"},{"year":"2017","key":"ref15","article-title":"Vector Supercomputer SX Series: SX-Aurora Tsubasa"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2017","author":"hennessy","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.2172\/1351758"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237038"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"260","DOI":"10.1145\/339647.339693","article-title":"Vector instruction set support for conditional operations","author":"smith","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.35"},{"year":"1984","key":"ref4","article-title":"Cray X-MP Series Model 48 Mainframe Reference Manual (HR-0097)"},{"key":"ref27","article-title":"The RISC-V instruction set manual, volume I: Base user-level ISA","volume":"116","author":"waterman","year":"2011"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/359327.359336"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1479992.1480022"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1968.229158"},{"key":"ref8","article-title":"Motorola AltiVec technology.","author":"fuller","year":"1998","journal-title":"Motorola Corporation"},{"year":"2012","key":"ref7","article-title":"Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture."},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277935"},{"article-title":"Vector Microprocessors","year":"1998","author":"asanovic?","key":"ref1"},{"year":"2015","key":"ref9","article-title":"Intel 64 and IA-32 architectures software developer's manual volume 2A: Instruction set reference"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237005"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00064"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/1543753.1543756"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151014"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1988.44642"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830796"},{"article-title":"Instruction Tables. Instruction latencies, throughputs and micro-operation breakdowns","year":"2018","author":"fog","key":"ref21"},{"key":"ref42","first-page":"603","article-title":"A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments","author":"wang","year":"2013","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Archit"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485954"},{"key":"ref41","first-page":"87","article-title":"FACOM VP-100\/200: Supercomputers with ease of use","volume":"2","year":"1985"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749714"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000080"},{"article-title":"Race to Exascale: Opportunities and Challenges","year":"2011","author":"sodani","key":"ref26"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310763"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s00607-015-0444-y"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/9575177\/09462482.pdf?arnumber=9462482","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T06:00:34Z","timestamp":1672552834000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9462482\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,1]]},"references-count":48,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2021.3091015","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"type":"print","value":"1045-9219"},{"type":"electronic","value":"1558-2183"},{"type":"electronic","value":"2161-9883"}],"subject":[],"published":{"date-parts":[[2022,4,1]]}}}