{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T14:06:34Z","timestamp":1782828394522,"version":"3.54.5"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2016YFB0200100"],"award-info":[{"award-number":["2016YFB0200100"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61732002"],"award-info":[{"award-number":["61732002"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62002186"],"award-info":[{"award-number":["62002186"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2022,8,1]]},"DOI":"10.1109\/tpds.2021.3120021","type":"journal-article","created":{"date-parts":[[2021,10,15]],"date-time":"2021-10-15T04:03:23Z","timestamp":1634270603000},"page":"1761-1774","source":"Crossref","is-referenced-by-count":3,"title":["iBalancer: Load-Aware in-Server Flow Scheduling for Sub-Millisecond Tail Latency"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0558-372X","authenticated-orcid":false,"given":"Qi","family":"Zhang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1829-2817","authenticated-orcid":false,"given":"Yi","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tao","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254766"},{"key":"ref38","article-title":"Mutilate load generator","year":"0"},{"key":"ref33","article-title":"82599 10 gbe controller datasheet","year":"2019"},{"key":"ref32","article-title":"How to set up intel ethernet flow director","year":"0"},{"key":"ref31","first-page":"667","article-title":"A high-speed load-balancer design with guaranteed per-connection-consistency","author":"barbette","year":"2020","journal-title":"Proc 17th USENIX Symp Netw Syst Des Implementation"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168870"},{"key":"ref37","year":"0"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3230543.3230560"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303977"},{"key":"ref34","year":"0"},{"key":"ref28","article-title":"DPDK release 18.11","year":"0"},{"key":"ref27","year":"0"},{"key":"ref29","year":"0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3341302.3342090"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3132747.3132756"},{"key":"ref20","first-page":"79","article-title":"Size-aware sharding for improving tail latencies in in-memory key-value stores","author":"didona","year":"2019","journal-title":"Proc 16th USENIX Symp Netw Syst Des Implementation"},{"key":"ref22","first-page":"489","article-title":"mTCP: A highly scalable user-level tcp stack for multicore systems","author":"jeong","year":"2014","journal-title":"Proc 11th USENIX Symp Netw Syst Des Implementation"},{"key":"ref21","year":"0"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303985"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3359989.3365412"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322227"},{"key":"ref25","first-page":"43","article-title":"StackMap: Low-latency networking with the OS stack and dedicated NICs","author":"yasukata","year":"2016","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/3341302.3342071"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/2391229.2391238"},{"key":"ref56","first-page":"667","article-title":"A high-speed load-balancer design with guaranteed per-connection-consistency","author":"barbette","year":"2020","journal-title":"Proc 17th USENIX Symp Netw Syst Des Implementation"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1145\/3419111.3421304"},{"key":"ref54","first-page":"863","article-title":"R2P2: Making RPCs first-class datacenter citizens","author":"kogias","year":"2019","journal-title":"Proc USENIX Annu Tech Conf"},{"key":"ref53","first-page":"1","article-title":"Datacenter RPCs can be general and fast","author":"kalia","year":"2019","journal-title":"Proc 16th USENIX Symp Netw Syst Des Implementation"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/3230543.3230564"},{"key":"ref10","year":"0"},{"key":"ref11","article-title":"Arrakis: The operating system as control plane","author":"peter","year":"2014","journal-title":"Proc USENIX Symp Oper Syst Des Implementation"},{"key":"ref40","first-page":"1","article-title":"A large scale analysis of hundreds of in-memory cache clusters at twitter","author":"yang","year":"2020","journal-title":"Proc 14th USENIX Symp Oper Syst Des Implementation"},{"key":"ref12","first-page":"49","article-title":"IX: A protected dataplane operating system for high throughput and low latency","author":"belay","year":"2014","journal-title":"Proc 11th USENIX Symp Oper Syst Des Implementation"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3132747.3132780"},{"key":"ref14","first-page":"345","article-title":"Shinjuku: Preemptive scheduling for ?second-scale tail latency","author":"kaffes","year":"2019","journal-title":"Proc 16th USENIX Symp Netw Syst Des Implementation"},{"key":"ref15","first-page":"361","article-title":"Shenango: Achieving high CPU efficiency for latency-sensitive datacenter workloads","author":"ousterhout","year":"2019","journal-title":"Proc 16th USENIX Symp Netw Syst Des Implementation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3317550.3321422"},{"key":"ref17","first-page":"281","article-title":"Caladan: Mitigating interference at microsecond timescales","author":"fried","year":"2020","journal-title":"Proc 14th USENIX Symp Oper Syst Des Implementation"},{"key":"ref18","first-page":"429","article-title":"MICA: A holistic approach to fast in-memory key-value storage","author":"lim","year":"2014","journal-title":"Proc 11th USENIX Symp Netw Syst Des Implementation"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750416"},{"key":"ref4","first-page":"135","article-title":"MegaPipe: A new programming interface for scalable network I\/O","author":"han","year":"2012","journal-title":"Proc USENIX Symp Oper Syst Des Implementation"},{"key":"ref3","first-page":"77","article-title":"AccelTCP: Accelerating network applications with stateful TCP offloading","author":"moon","year":"2020","journal-title":"Proc 17th USENIX Symp Netw Syst Des Implementation"},{"key":"ref6","first-page":"1","article-title":"FlexNIC: Rethinking network DMA","author":"kaufmann","year":"2015","journal-title":"Proc 15th Workshop Hot Topics Oper Syst"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378528"},{"key":"ref8","year":"0"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872367"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2980024.2872391"},{"key":"ref9","year":"0"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2806777.2806848"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592821"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168870"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/3365609.3365856"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3343180.3343184"},{"key":"ref41","first-page":"265","article-title":"TensorFlow: A system for large-scale machine learning","author":"abadi","year":"2016","journal-title":"Proc 12th USENIX Symp Oper Syst Des Implementation"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2741948.2741967"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304070"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/71\/9642402\/09573311.pdf?arnumber=9573311","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T17:55:55Z","timestamp":1649440555000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9573311\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,1]]},"references-count":56,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2021.3120021","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,8,1]]}}}