{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T16:02:12Z","timestamp":1774540932997,"version":"3.50.1"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62432005"],"award-info":[{"award-number":["62432005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62302270"],"award-info":[{"award-number":["62302270"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100007129","name":"Natural Science Foundation of Shandong Province","doi-asserted-by":"publisher","award":["ZR20220F003"],"award-info":[{"award-number":["ZR20220F003"]}],"id":[{"id":"10.13039\/501100007129","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100007129","name":"Natural Science Foundation of Shandong Province","doi-asserted-by":"publisher","award":["ZR2024MF099"],"award-info":[{"award-number":["ZR2024MF099"]}],"id":[{"id":"10.13039\/501100007129","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Department of Science &#x0026; Technology of Shandong Province","award":["SYS202201"],"award-info":[{"award-number":["SYS202201"]}]},{"name":"Quan Cheng Laboratory","award":["QCLZD202302"],"award-info":[{"award-number":["QCLZD202302"]}]},{"name":"Taishan Scholars Program","award":["tsqn202211281"],"award-info":[{"award-number":["tsqn202211281"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1109\/tpds.2025.3555968","type":"journal-article","created":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T18:19:04Z","timestamp":1743531544000},"page":"1146-1160","source":"Crossref","is-referenced-by-count":1,"title":["WCET Estimation for CNN Inference on FPGA SoC With Multi-DPU Engines"],"prefix":"10.1109","volume":"36","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2615-2603","authenticated-orcid":false,"given":"Wei","family":"Zhang","sequence":"first","affiliation":[{"name":"School of Cyber Science and Technology, Shandong University, Qingdao, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-3679-8359","authenticated-orcid":false,"given":"Yunlong","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Cyber Science and Technology, Shandong University, Qingdao, China"}]},{"given":"Xiao","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Cyber Science and Technology, Shandong University, Qingdao, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3775-911X","authenticated-orcid":false,"given":"Nan","family":"Guan","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Hong Kong, SAR, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3298-3817","authenticated-orcid":false,"given":"Naijun","family":"Zhan","sequence":"additional","affiliation":[{"name":"School of Computer Science and Key Laboratory of High Confidence Software Technology, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6186-5399","authenticated-orcid":false,"given":"Lei","family":"Ju","sequence":"additional","affiliation":[{"name":"Quan Cheng Laboratory, Jinan, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3368089.3417063"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3289185"},{"key":"ref3","article-title":"Vitis AI user guide (UG1414 v2. 0)","year":"2022","journal-title":"AMD Xilinx"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00018"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT56656.2022.9974299"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3323212"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS52674.2021.00047"},{"key":"ref9","article-title":"Deep learning on FPGAs: Past, present, and future","author":"Lacey","year":"2016"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2865896"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3000118"},{"key":"ref13","volume-title":"The ZYNQ Book","author":"Louise Crockett","year":"2015"},{"key":"ref14","article-title":"AMBA AXI and ACE protocol specification","year":"2011","journal-title":"AXI4_specification.pdf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref17","article-title":"YOLOv3: An incremental improvement","author":"Redmon","year":"2018"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.350"},{"key":"ref19","first-page":"23:1","article-title":"Generating and exploiting deep learning variants to increase heterogeneous resource utilization in the nvidia xavier","volume-title":"Proc. 31st Euromicro Conf. Real-Time Syst.","author":"Pujol"},{"key":"ref20","article-title":"DPUCZDX8G for Zynq ultrascale MPSoCs product guide (PG338 v3.4)","year":"2023"},{"key":"ref21","article-title":"YOLOv4: Optimal speed and accuracy of object detection","author":"Bochkovskiy","year":"2020"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2930577"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530613"},{"key":"ref24","article-title":"AXI performance monitor v5.0 LogiCORE IP product guide (PG037 v5.0)","year":"2017"},{"key":"ref25","article-title":"SqueezeNet: Alexnet-level accuracy with 50x fewer parameters and $< $<0.5mb model size","author":"Iandola","year":"2016"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2017.215"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.l007\/978-3-319-46448-0_2"},{"key":"ref28","article-title":"System integrated logic analyzer v1.1 LogiCORE IP product guide (PG261 v1.1)","year":"2017"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00030"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2941250"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2905242"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/FPL53798.2021.00019"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2988311"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00084"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2009.55"},{"key":"ref36","first-page":"7:1","article-title":"Towards multicore wcet analysis","volume-title":"Proc. 17th Int. Workshop Worst-Case Execution Time Anal.","author":"Wegener"},{"key":"ref37","first-page":"3:1","article-title":"HWP: Hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems","volume-title":"Proc. 30th Euromicro Conf. Real-Time Syst.","author":"Benedicte"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742973"},{"key":"ref39","first-page":"12:1","article-title":"Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs","volume-title":"Proc. 32nd Euromicro Conf. Real-Time Syst.","author":"Restuccia"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473925"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2020.3017455"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3214117"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/71\/10969501\/10946206.pdf?arnumber=10946206","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T17:40:23Z","timestamp":1745257223000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10946206\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6]]},"references-count":42,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2025.3555968","relation":{},"ISSN":["1045-9219","1558-2183","2161-9883"],"issn-type":[{"value":"1045-9219","type":"print"},{"value":"1558-2183","type":"electronic"},{"value":"2161-9883","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,6]]}}}