{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:53:58Z","timestamp":1759146838906},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Rel."],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/tr.2014.2316952","type":"journal-article","created":{"date-parts":[[2014,4,23]],"date-time":"2014-04-23T20:09:50Z","timestamp":1398283790000},"page":"661-675","source":"Crossref","is-referenced-by-count":18,"title":["Dynamic Function Replacement for System-on-Chip Security in the Presence of Hardware-Based Attacks"],"prefix":"10.1109","volume":"63","author":[{"given":"Lok-Won","family":"Kim","sequence":"first","affiliation":[]},{"given":"John D.","family":"Villasenor","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","year":"2008","journal-title":"?Clock domain crossing (CDC) Design & verification techniques using SystemVerilog Sunburst Design ?"},{"key":"ref32","year":"1999","journal-title":"?ARM AMBA specification (rev 2 0) ?"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.50"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICEMI.2007.4350589"},{"key":"ref35","year":"2009","journal-title":"?XILINX Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode ?"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231828"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2060375"},{"key":"ref11","article-title":"Integrated circuit security?New threats and solutions","author":"abramovici","year":"2009","journal-title":"Proc Cyber Security Inf Infrastructure Res Workshop"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5224990"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2010.5560200"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2010.19"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/24.814517"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2006.54"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859319"},{"key":"ref18","first-page":"120","article-title":"An 8<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\,\\times\\,$<\/tex><\/formula>8 run-time reconfigurable FPGA embedded in a SoC","author":"chaudhuri","year":"2008","journal-title":"Proc IEEE-ACM Design Automation Conf"},{"key":"ref19","first-page":"979","article-title":"Cluster-based hybrid reconfigurable architecture for autoadaptive SOCs","author":"jhang","year":"2007","journal-title":"Proc 14th IEEE Int Conf Electron Circuits Syst (ICECS 2007)"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"196","DOI":"10.1145\/337292.337384","article-title":"Formal verification of an IBM coreconnect processor local bus arbiter care","author":"goel","year":"2000","journal-title":"Proc 37th Design Autom Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2010.2061228"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/40.612211"},{"key":"ref3","first-page":"51","article-title":"Hardware Trojan detection using path delay fingerprint","author":"jin","year":"2008","journal-title":"IEEE Intl Workshop on Hardware-oriented Security and Trust (HOST'08)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2093547"},{"key":"ref29","first-page":"305","article-title":"HW\/SW interface synthesis based on Avalon bus specification for Nios-oriented SoC design","author":"lin","year":"2005","journal-title":"Proc IEEE Int Conf Field-Programmable Technol"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2010.5513122"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569378"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559037"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MILCOM.2009.5379966"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873611"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568636"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915439"},{"key":"ref21","year":"1999","journal-title":"?ATMEL Atmel's embedded FPGA cores enable programmable ASICs ASSPs ?"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012717"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.77"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISICIR.2007.4441899"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377997"}],"container-title":["IEEE Transactions on Reliability"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/24\/6823191\/06804702.pdf?arnumber=6804702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:56:44Z","timestamp":1642006604000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6804702\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":35,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tr.2014.2316952","relation":{},"ISSN":["0018-9529","1558-1721"],"issn-type":[{"value":"0018-9529","type":"print"},{"value":"1558-1721","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,6]]}}}