{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T03:13:35Z","timestamp":1777605215697,"version":"3.51.4"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2015,6,1]],"date-time":"2015-06-01T00:00:00Z","timestamp":1433116800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea (NRF)","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Korea government (MEST)","award":["2012R1A2A1A03006255"],"award-info":[{"award-number":["2012R1A2A1A03006255"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Rel."],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/tr.2015.2410274","type":"journal-article","created":{"date-parts":[[2015,3,16]],"date-time":"2015-03-16T14:46:35Z","timestamp":1426517195000},"page":"586-595","source":"Crossref","is-referenced-by-count":18,"title":["A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories"],"prefix":"10.1109","volume":"64","author":[{"given":"Wooheon","family":"Kang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Changwook","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyunyul","family":"Lim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2003513"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.62"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2222882"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6165054"},{"key":"ref14","first-page":"23","article-title":"3D-IC BISR for stacked memories using cross-die spares","author":"chi","year":"2012","journal-title":"Proc 2012 Int Symp VLSI Design Automation Test (VLSI-DAT)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.12.017"},{"key":"ref16","first-page":"1","article-title":"Global built-in self-repair for 3D memories with redundancy sharing and parallel testing","author":"wang","year":"2012","journal-title":"Proc 2011 IEEE Int 3D System Integration Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2296538"},{"key":"ref19","first-page":"8","article-title":"Economics modeling for the determination of optimal known good die strategies","author":"dislis","year":"1995","journal-title":"Proc 1995 IEEE Multi-Chip Module Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034408"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref27","author":"van de goor","year":"1991","journal-title":"Testing Semiconductor Memories Theory and Practice"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005988"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.10"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.877252"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2062830"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007473"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref22","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"tarr","year":"1984","journal-title":"Electronics"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.144"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050655"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2288637"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030229"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1147\/rd.243.0398"}],"container-title":["IEEE Transactions on Reliability"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/24\/7115294\/07061513.pdf?arnumber=7061513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:45:11Z","timestamp":1641987911000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7061513\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":27,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tr.2015.2410274","relation":{},"ISSN":["0018-9529","1558-1721"],"issn-type":[{"value":"0018-9529","type":"print"},{"value":"1558-1721","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6]]}}}