{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,6]],"date-time":"2024-07-06T16:00:15Z","timestamp":1720281615430},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2009,11,1]],"date-time":"2009-11-01T00:00:00Z","timestamp":1257033600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Signal Process."],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1109\/tsp.2009.2024870","type":"journal-article","created":{"date-parts":[[2009,6,10]],"date-time":"2009-06-10T14:45:25Z","timestamp":1244645125000},"page":"4538-4547","source":"Crossref","is-referenced-by-count":6,"title":["Optimizing Scheduling and Intercluster Connection for Application-Specific DSP Processors"],"prefix":"10.1109","volume":"57","author":[{"family":"Cathy Qun Xu","sequence":"first","affiliation":[]},{"family":"Chun Jason Xue","sequence":"additional","affiliation":[]},{"family":"Jingtong Hu","sequence":"additional","affiliation":[]},{"given":"E.H.-M.","family":"Sha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","first-page":"715","article-title":"dspstone: a dsp-oriented benchmarking methodology","author":"zivojnovic","year":"1994","journal-title":"Proc Int Conf Signal Process Appl Technol"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2007.94"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/54.844333"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.259938"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/BF02579150"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/71.503776"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1023\/A:1019076003163"},{"key":"ref15","article-title":"a new clustering algorithm for scheduling task graphs with large communication delays","author":"lepre","year":"2002","journal-title":"Proc Int Parallel Distrib Process Symp"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/92.678867"},{"key":"ref17","author":"papadimitriou","year":"1998","journal-title":"Combinational Optimization Algorithms and Complexity"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824366"},{"key":"ref19","article-title":"clustering on the move","author":"roos","year":"2002","journal-title":"Proc 1st Int Conf Massively Parallel Comput Syst"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.880026"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/43.594829"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-006-0034-5"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/71.640018"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/28869.28874"},{"key":"ref29","author":"yu","year":"1984","journal-title":"LU decomposition on a multiprocessing system with communication delay"},{"key":"ref5","first-page":"203","article-title":"Lx: a technology platform for customizable VLIW embedded processing","author":"faraboschi","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref8","first-page":"308","article-title":"unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures","author":"zer","year":"1998","journal-title":"Proc 31st Annu ACM\/IEEE Int Symp Microarchitecture"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1188275.1188276"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"118","DOI":"10.1145\/500001.500029","article-title":"phase coupled operation assignment for vliw processors with distributed register files","author":"bekooij","year":"2001","journal-title":"Proc Int Symp Syst Synthesis"},{"key":"ref9","year":"2006","journal-title":"TMS320C6000 CPU and Instruction Set Reference Guide"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.20"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSS.2000.874027"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1124713.1124724"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.892215"},{"key":"ref24","author":"sriram","year":"2000","journal-title":"Embedded Multiprocessors Scheduling and Synchronization"},{"key":"ref23","first-page":"21","author":"song","year":"1998","journal-title":"Demystifying EPIC and IA-64"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.913721"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183552"}],"container-title":["IEEE Transactions on Signal Processing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/78\/5286803\/05071167.pdf?arnumber=5071167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:50:57Z","timestamp":1633909857000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5071167\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":31,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tsp.2009.2024870","relation":{},"ISSN":["1053-587X","1941-0476"],"issn-type":[{"value":"1053-587X","type":"print"},{"value":"1941-0476","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,11]]}}}