{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:12:42Z","timestamp":1730301162108,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/tsp.2018.8441241","type":"proceedings-article","created":{"date-parts":[[2018,8,23]],"date-time":"2018-08-23T22:08:21Z","timestamp":1535062101000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework"],"prefix":"10.1109","author":[{"given":"Michael","family":"Dossis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgios","family":"Dimitriou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691121"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927490"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2228270"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/SEEDA-CECNSM.2017.8088235"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.27"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8_9"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027087"},{"key":"ref6","article-title":"Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow","author":"gupta","year":"2003","journal-title":"Center for Embedded Computer Systems Technical Report #03–14 University of California at Irvine"},{"key":"ref5","article-title":"Experimenting with a High-Level Synthesis System Front End","author":"dimitriou","year":"0","journal-title":"PACET 2015 Ioannina May 2015 also to appear in Journal of Engineering Science and Technology Review"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435271"},{"key":"ref7","article-title":"Coupling Loop Transformations and High-Level Synthesis","author":"plesco","year":"2008","journal-title":"RenPar'18 \/ SympA'2008 \/ CFSE'6"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/54.386007"},{"key":"ref1","first-page":"929","article-title":"A Formal Design Framework to Generate Coprocessors with Implementation Options","volume":"2","author":"dossis","year":"2011","journal-title":"International Journal of Research and Reviews in Computer Science IJRRCS"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228586"}],"event":{"name":"2018 41st International Conference on Telecommunications and Signal Processing (TSP)","start":{"date-parts":[[2018,7,4]]},"location":"Athens","end":{"date-parts":[[2018,7,6]]}},"container-title":["2018 41st International Conference on Telecommunications and Signal Processing (TSP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8419443\/8441166\/08441241.pdf?arnumber=8441241","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T12:33:35Z","timestamp":1643200415000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8441241\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/tsp.2018.8441241","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}