{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:32:47Z","timestamp":1761323567608},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2008,7,1]],"date-time":"2008-07-01T00:00:00Z","timestamp":1214870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2008,7]]},"DOI":"10.1109\/tvlsi.2008.2000461","type":"journal-article","created":{"date-parts":[[2008,7,3]],"date-time":"2008-07-03T14:37:20Z","timestamp":1215095840000},"page":"874-881","source":"Crossref","is-referenced-by-count":16,"title":["New Non-Volatile Memory Structures for FPGA Architectures"],"prefix":"10.1109","volume":"16","author":[{"given":"David","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyu","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John D.","family":"Villasenor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065820"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2004.30"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.885731"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2004.15"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.857180"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.62145"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2003.1221204"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2004.1345401"},{"key":"ref6","year":"2005","journal-title":"Method of manufacturing self-aligned non-volatile memory device"},{"key":"ref5","year":"2005","journal-title":"Non-volatile memory device"},{"key":"ref8","year":"2006","journal-title":"ProASIC3 Flash family FPGAs datasheet Ver 0 6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2006.307589"},{"key":"ref2","first-page":"252","article-title":"a highly scalable split-gate sonos flash memory with programmable-pass and pure-select transistors for sub-90-nm technology","author":"lee","year":"2004","journal-title":"Proc Int Conf Solid-State Devices Mater"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/55.701434"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4553745\/04539803.pdf?arnumber=4539803","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:06Z","timestamp":1638219366000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4539803\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,7]]},"references-count":15,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2000461","relation":{},"ISSN":["1063-8210"],"issn-type":[{"value":"1063-8210","type":"print"}],"subject":[],"published":{"date-parts":[[2008,7]]}}}