{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T18:31:16Z","timestamp":1780511476821,"version":"3.54.1"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2008,11,1]],"date-time":"2008-11-01T00:00:00Z","timestamp":1225497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/tvlsi.2008.2000866","type":"journal-article","created":{"date-parts":[[2008,9,30]],"date-time":"2008-09-30T14:56:19Z","timestamp":1222786579000},"page":"1441-1453","source":"Crossref","is-referenced-by-count":75,"title":["Systematic Software-Based Self-Test for Pipelined Processors"],"prefix":"10.1109","volume":"16","author":[{"given":"D.","family":"Gizopoulos","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Psarakis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Hatzimihail","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Maniatakos","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A.","family":"Paschalis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A.","family":"Raghunathan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Ravi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.59"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.886412"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583987"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297676"},{"key":"ref14","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-2801-4","author":"gizopoulos","year":"2004","journal-title":"Embedded Processor-Based Self-Test"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/52.57892"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/296333.296345"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2000.855288"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277905"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1994.629879"},{"key":"ref28","author":"patterson","year":"2005","journal-title":"Computer Organization and Design The Hardware\/Software Interface"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041810"},{"key":"ref27","year":"2008","journal-title":"OpenRISC1200"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766644"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915026"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297675"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219068"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.913755"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743296"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.68"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805650"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1995.249960"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379072"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781307"},{"key":"ref24","author":"mishra","year":"2005","journal-title":"Functional Verification of Programmable Embedded Architectures A Top-Down Approach"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268846"},{"key":"ref26","year":"2008","journal-title":"miniMIPS CPU"},{"key":"ref25","year":"2008","journal-title":"ArchC architecture description language"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4655424\/04636714.pdf?arnumber=4636714","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:07Z","timestamp":1638219367000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4636714\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":28,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2000866","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,11]]}}}