{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,8]],"date-time":"2024-06-08T19:20:53Z","timestamp":1717874453485},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/tvlsi.2008.2001238","type":"journal-article","created":{"date-parts":[[2008,12,17]],"date-time":"2008-12-17T21:08:28Z","timestamp":1229548108000},"page":"1-11","source":"Crossref","is-referenced-by-count":6,"title":["Wire Topology Optimization for Low Power CMOS"],"prefix":"10.1109","volume":"17","author":[{"given":"P.","family":"Zuber","sequence":"first","affiliation":[]},{"given":"O.","family":"Bahlous","sequence":"additional","affiliation":[]},{"given":"T.","family":"Ilnseher","sequence":"additional","affiliation":[]},{"given":"M.","family":"Ritter","sequence":"additional","affiliation":[]},{"given":"W.","family":"Stechele","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/11556930_69"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1080\/00207168308803365"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-663-09886-7"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1117\/12.724139"},{"key":"ref14","author":"rockafellar","year":"1972","journal-title":"Convex Analysis"},{"key":"ref15","author":"niskanen","year":"2003","journal-title":"?Cliquer user's guide version 1 0 ?"},{"key":"ref16","year":"0","journal-title":"?IWLS'05 Benchmarks ?"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref18","author":"allan","year":"2006","journal-title":"?EYES User manual ?"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5685-5_3"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817126"},{"key":"ref6","first-page":"24","article-title":"timing preservation in wire spreading utilized for yield improvement","author":"serdar","year":"2006","journal-title":"Proc IEEE Int Conf Integr Circuit Des Technol (ICICDT)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643615"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/764808.764859"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998264"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref9","first-page":"4","article-title":"simultaneous wire permutation, inversion, and spacing with genetic algorithm for energy-efficient bus design","author":"ruan","year":"2005","journal-title":"Proc 19th IEEE Symp Int Parallel Distrib Process"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4717837\/04711069.pdf?arnumber=4711069","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:07Z","timestamp":1638219367000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4711069\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":18,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2001238","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,1]]}}}