{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T20:20:35Z","timestamp":1694636435669},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2009,9,1]],"date-time":"2009-09-01T00:00:00Z","timestamp":1251763200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,9]]},"DOI":"10.1109\/tvlsi.2008.2002429","type":"journal-article","created":{"date-parts":[[2009,3,24]],"date-time":"2009-03-24T19:41:00Z","timestamp":1237923660000},"page":"1247-1259","source":"Crossref","is-referenced-by-count":15,"title":["CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays"],"prefix":"10.1109","volume":"17","author":[{"given":"J.O.","family":"Filho","sequence":"first","affiliation":[]},{"given":"S.","family":"Masekowsky","sequence":"additional","affiliation":[]},{"given":"T.","family":"Schweizer","sequence":"additional","affiliation":[]},{"given":"W.","family":"Rosenstiel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","year":"2008","journal-title":"System Generator for DSP"},{"key":"ref31","doi-asserted-by":"crossref","DOI":"10.1145\/1028176.1006733","article-title":"evaluation of the raw microprocessor: an exposed-wire-delay architecture for ilp and streams","author":"taylor","year":"2004","journal-title":"SIGARCH Comput Architecture News"},{"key":"ref30","first-page":"1997","article-title":"dynamically reconfigurable processor implemented with ipflex's dapdna technology","volume":"e87d","author":"sugawara","year":"2004","journal-title":"IEICE Trans Inf Syst"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597161"},{"key":"ref11","first-page":"458","article-title":"expression: a language for architecture exploration through compiler\/simulator retargetability","author":"halambi","year":"1999","journal-title":"Proc Design Automation Test in Europe"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICVC.1999.820839"},{"key":"ref13","first-page":"141","article-title":"using the kressarray for reconfigurable computing","volume":"3526","author":"hartenstein","year":"1998","journal-title":"Configurable Computing Technol Appl"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-4538-2"},{"key":"ref15","article-title":"an architecture description language for massively parallel processor architectures","author":"kupriyanov","year":"2006","journal-title":"Proc GIITGGMM"},{"key":"ref16","year":"2008","journal-title":"SimulinkSimulation and model-based design"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_7"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269063"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337583"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024499601571"},{"key":"ref27","first-page":"141","article-title":"efficient mapping and functional verification of parallel algorithms on a multi-context reconfigurable architecture","author":"rullmann","year":"2007","journal-title":"Proc 20th Int Conf Architecture Comput Syst \/Workshop Dynamically Reconfigurable Syst"},{"key":"ref3","author":"bashford","year":"1994","journal-title":"The MIMOLA Language Version 4 1"},{"key":"ref6","first-page":"33","article-title":"designing with systemc: multi-paradigm modeling and simulation performance evaluation","author":"charest","year":"2002","journal-title":"Proc Int Hardware Description Language (HDL) Conf"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2004.1411138"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-71431-6_1"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470354"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1109\/FPGA.1996.242438","article-title":"dpga utilization and application","author":"dehon","year":"1996","journal-title":"Fourth International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.29"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/502217.502234"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-005-7301-0"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/972627.972633"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1997.600261"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045071"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-04267-0"},{"key":"ref23","first-page":"328","article-title":"a dynamically reconfigurable processor architecture","author":"motomura","year":"2002","journal-title":"Microprocessor Forum"},{"key":"ref26","article-title":"a new design approach for processor-like reconfigurable hardware","author":"oppold","year":"2004","journal-title":"Proc Euro DesignCon"},{"key":"ref25","first-page":"157","article-title":"crcconcepts and evaluation of processor-like reconfigurable architectures","volume":"49","author":"oppold","year":"2007","journal-title":"Inf Technol"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5208586\/04804670.pdf?arnumber=4804670","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:58Z","timestamp":1633910398000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4804670\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":32,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2002429","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,9]]}}}