{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:10:56Z","timestamp":1742386256496},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/tvlsi.2008.2002459","type":"journal-article","created":{"date-parts":[[2008,12,4]],"date-time":"2008-12-04T16:14:03Z","timestamp":1228407243000},"page":"80-91","source":"Crossref","is-referenced-by-count":39,"title":["Fast Configurable-Cache Tuning With a Unified Second-Level Cache"],"prefix":"10.1109","volume":"17","author":[{"given":"A.","family":"Gordon-Ross","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Vahid","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.D.","family":"Dutt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804107"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159709"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268850"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195540"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1145\/344166.344610","article-title":"a low power unified cache architecture providing power and performance flexibility","author":"malik","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765946"},{"key":"ref17","year":"0","journal-title":"?MIPS homepage ?"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CODES.2002.1003603"},{"key":"ref19","author":"reinman","year":"1999","journal-title":"?Cacti2 0 An integraded cache timing and power model ?"},{"key":"ref4","year":"2008","journal-title":"?Arm homepage ?"},{"key":"ref3","year":"2008","journal-title":"?Arc Cores homepage ?"},{"key":"ref6","author":"burger","year":"2000","journal-title":"?Evaluating future microprocessors The Simplescalar toolset ?"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360153"},{"key":"ref8","year":"2008","journal-title":"?The embedded microprocessor benchmark consortium ?"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303102"},{"key":"ref2","year":"2001","journal-title":"?Nios embedded processor system ?"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515691"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"ref20","article-title":"low power design techniques for microprocessors","author":"segars","year":"2001","journal-title":"IEEE Int Solid-State Circuits Conf"},{"key":"ref22","year":"2008","journal-title":"?Xtensa processor generator ?"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261391"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305188"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268840"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993405"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4717837\/04689316.pdf?arnumber=4689316","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:08Z","timestamp":1638219368000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4689316\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":26,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2002459","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,1]]}}}