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VLSI Syst."],"published-print":{"date-parts":[[2009,9]]},"abstract":"<jats:p>This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb\/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ\/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.<\/jats:p>","DOI":"10.1109\/tvlsi.2008.2002682","type":"journal-article","created":{"date-parts":[[2009,3,12]],"date-time":"2009-03-12T13:47:20Z","timestamp":1236865640000},"page":"1267-1274","source":"Crossref","is-referenced-by-count":11,"title":["A 32-Gb\/s On-Chip Bus With Driver Pre-Emphasis Signaling"],"prefix":"10.1109","volume":"17","author":[{"given":"Liang","family":"Zhang","sequence":"first","affiliation":[]},{"given":"John M.","family":"Wilson","sequence":"additional","affiliation":[]},{"given":"Rizwan","family":"Bashirullah","sequence":"additional","affiliation":[]},{"given":"Lei","family":"Luo","sequence":"additional","affiliation":[]},{"given":"Jian","family":"Xu","sequence":"additional","affiliation":[]},{"given":"Paul D.","family":"Franzon","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Digital Systems Engineering","year":"1997","author":"dally","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/16.249433"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.75050"},{"key":"ref13","first-page":"315","article-title":"differential current-mode signaling for robust and power efficient on-chip global interconnects","author":"zhang","year":"2005","journal-title":"Elect Performance Electron Packag"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2003.1221224"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.804706"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/92.805751"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/5.920582"},{"journal-title":"The SimpleScalar tool set version 2 0","year":"1997","author":"burger","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696207"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810060"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.862351"},{"key":"ref5","first-page":"253","article-title":"a 100 mw 9.6 gb\/s transceiver in 90 nm cmos for next-generation memory interfaces","volume":"4 5","author":"prete","year":"2006","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859880"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857351"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/81.841866"},{"journal-title":"Interconnections and Packaging for VLSI","year":"1990","author":"bakoglu","key":"ref1"},{"key":"ref9","first-page":"265","article-title":"a 32 gb\/s on-chip bus with driver pre-emphasis signaling","volume":"p 16","author":"zhang","year":"2006","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"1996","author":"rabaey","key":"ref20"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/iel5\/92\/5208586\/04799215.pdf?arnumber=4799215","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5208586\/04799215.pdf?arnumber=4799215","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:54Z","timestamp":1633910394000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4799215\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":20,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2009,9]]}},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2002682","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2009,9]]}}}