{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,4,25]],"date-time":"2024-04-25T04:38:57Z","timestamp":1714019937995},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2009,2,1]],"date-time":"2009-02-01T00:00:00Z","timestamp":1233446400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,2]]},"DOI":"10.1109\/tvlsi.2008.2003236","type":"journal-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T20:58:26Z","timestamp":1228942706000},"page":"194-206","source":"Crossref","is-referenced-by-count":20,"title":["A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy"],"prefix":"10.1109","volume":"17","author":[{"given":"K.","family":"Bhattacharya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Ranganathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Soontae Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/951710.951750"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2003.1209939"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2006.55"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.856487"},{"key":"ref31","first-page":"259","article-title":"historical trend in alpha-particle induced soft error rates of the alpha microprocessor","author":"seifert","year":"2001","journal-title":"Proc Int Reliab Phys Symp"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380862"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006212"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"ref35","year":"2005","journal-title":"?UltraSparc T1 ?"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/4.568829"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1225959"},{"key":"ref11","article-title":"mitigating multi-bit soft errors in l1 caches using last-store prediction","author":"gold","year":"2007","journal-title":"Federated Comput Res Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1998.650559"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/23.903813"},{"key":"ref14","first-page":"1","article-title":"the microarchitecture of the pentium 4 processor","volume":"1","author":"hinton","year":"2001","journal-title":"Intel Technol J"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.43"},{"key":"ref16","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1525-4","author":"jha","year":"1990","journal-title":"Testing and Reliable Design of CMOS Circuits"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1995.528827"},{"key":"ref18","first-page":"61","article-title":"scaling trends of cosmic ray induced soft errors in static latchesbeyond 0.18","author":"karnik","year":"2001","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/40.877951"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.18"},{"key":"ref27","author":"phelan","year":"2003","journal-title":"?Addressing soft errors in arm core-based SOC ?"},{"key":"ref3","first-page":"224","article-title":"improving the reliability of on-chip l2 cache using redundancy","author":"bhattacharya","year":"2007","journal-title":"Proc ICCD"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997876"},{"key":"ref29","author":"reinman","year":"1999","journal-title":"?An integrated cache timing and power model ?"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"ref8","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744314"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430581"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref1","year":"2000","journal-title":"? CPU 2000 Benchmarks ?"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898054"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765955"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.70"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269335"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2006.31"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2004.1276550"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4749486\/04703180.pdf?arnumber=4703180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:00:24Z","timestamp":1633910424000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4703180\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,2]]},"references-count":39,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2003236","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,2]]}}}