{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:35:02Z","timestamp":1781886902460,"version":"3.54.5"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/tvlsi.2008.2006846","type":"journal-article","created":{"date-parts":[[2009,3,24]],"date-time":"2009-03-24T19:41:00Z","timestamp":1237923660000},"page":"15-28","source":"Crossref","is-referenced-by-count":39,"title":["Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture"],"prefix":"10.1109","volume":"18","author":[{"given":"Yoonjin","family":"Kim","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rabi N.","family":"Mahapatra","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173050"},{"key":"ref11","first-page":"57","article-title":"regular mapping for coarse-grained reconfigurable architectures","author":"hanning","year":"2004","journal-title":"Proc IEEE Int Conf Acoust Speech Signal Process"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2003.1183360"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2004.42"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"106","DOI":"10.1109\/FPL.2005.1515707","article-title":"custom implementation of the coarse-grained reconfigurable adres architecture for multimedia purposes","author":"vererdas","year":"2005","journal-title":"Proc Int Conf Field Program Logic Appl"},{"key":"ref16","first-page":"227","article-title":"design and evaluation of coarse-grained reconfigurable architecture","author":"kim","year":"2004","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref17","first-page":"12","article-title":"resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization","author":"kim","year":"2005","journal-title":"Proc Des Autom Test Eur Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165646"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2002.1012767"},{"key":"ref28","year":"0","journal-title":"Model Technology Corporation"},{"key":"ref4","article-title":"analysis of the performance of coarse-grain reconfigurable architectures with different processing element configurations","author":"nikhil","year":"2003","journal-title":"Workshop Appl Specific Process"},{"key":"ref27","year":"0","journal-title":"Taiwan Semi Manufacturing Company Ltd"},{"key":"ref3","first-page":"1224","article-title":"design methodology for a tightly coupled vliw\/reconfigurable matrix architecture: a case study","author":"bingfeng","year":"2004","journal-title":"Proc Des Autom Test Eur Conf"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IWV.1999.760456"},{"key":"ref5","article-title":"energy-aware interconnect-exploration of coarse-grained reconfigurable processors","author":"andy","year":"2005","journal-title":"Workshop Appl Specific Process"},{"key":"ref8","author":"jong-eun","year":"2002","journal-title":"Mapping loops on coarse-grained reconfigurable architectures using memory operation sharing"},{"key":"ref7","first-page":"148a","article-title":"mapping of regular nested loop programs to coarse-grained reconfigurable arraysconstraints and methodology","author":"frank","year":"2004","journal-title":"Proc IEEE Int Parallel Distrib Process Symp"},{"key":"ref2","first-page":"163","article-title":"kressarray xplorer: a new cad environment to optimize reconfigurable datapath array architectures","author":"reiner","year":"2000","journal-title":"Proc Asia South Pacific Des Autom Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/780731.780758"},{"key":"ref1","first-page":"642","article-title":"a decade of reconfigurable computing: a visionary retrospective","author":"reiner","year":"2001","journal-title":"Proc Des Autom Test Eur Conf"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707876"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303136"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195507"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IWRSP.2000.855217"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_23"},{"key":"ref26","year":"0","journal-title":"Synopsys Corporation"},{"key":"ref25","year":"0","journal-title":"ARM Corporation"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5357587\/04804672.pdf?arnumber=4804672","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:47Z","timestamp":1633910387000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4804672\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":28,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2006846","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,1]]}}}