{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:32:39Z","timestamp":1781836359220,"version":"3.54.5"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/tvlsi.2008.2008453","type":"journal-article","created":{"date-parts":[[2008,12,10]],"date-time":"2008-12-10T20:58:26Z","timestamp":1228942706000},"page":"33-44","source":"Crossref","is-referenced-by-count":105,"title":["Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating"],"prefix":"10.1109","volume":"17","author":[{"given":"H.","family":"Mahmoodi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"V.","family":"Tirumalashetty","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Cooke","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"K.","family":"Roy","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/81.841927"},{"key":"ref11","first-page":"249","article-title":"empirical evaluation of timing and power in resonant clock distribution","volume":"2","author":"chueh","year":"2004","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1145\/871506.871524","article-title":"energy recovery clocking scheme and flip-flops for ultra low-energy applications","author":"cooke","year":"2003","journal-title":"Proc Int Symp Low Power Electron Des"},{"key":"ref13","first-page":"1141","article-title":"clock gating and negative edge triggering for energy recovery clock","author":"tirumalashetty","year":"2001","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922182"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.938376"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.668997"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488543"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.921153"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/92.335009"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885041"},{"key":"ref9","author":"rabaey","year":"1996","journal-title":"Digital Integrated Circuits"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4717837\/04703179.pdf?arnumber=4703179","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:08Z","timestamp":1638219368000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4703179\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":13,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2008453","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,1]]}}}