{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T18:56:50Z","timestamp":1761418610497},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/tvlsi.2008.2010324","type":"journal-article","created":{"date-parts":[[2009,6,25]],"date-time":"2009-06-25T16:28:31Z","timestamp":1245947311000},"page":"246-255","source":"Crossref","is-referenced-by-count":17,"title":["An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs"],"prefix":"10.1109","volume":"18","author":[{"given":"Da-Cheng","family":"Juan","sequence":"first","affiliation":[]},{"given":"Yu-Ting","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ming-Chao","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Shih-Chieh","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"cormen","year":"2001","journal-title":"Introduction to Algorithm 2nd"},{"key":"ref11","author":"keating","year":"2007","journal-title":"Low Power Methodology Manual For System-on-Chip Design"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231828"},{"key":"ref13","first-page":"51","article-title":"estimation of maximum power-up current","author":"li","year":"2002","journal-title":"Proc ASP-DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.832939"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981101"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542325"},{"key":"ref17","first-page":"25","article-title":"wake-up scheduling in mtcmos circuits using successive relaxation to minimize ground bounce","volume":"3","author":"ramalingam","year":"2007","journal-title":"ASP J Low Power Electron"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996693"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012673"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065716"},{"key":"ref5","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146945"},{"key":"ref7","first-page":"777","article-title":"an efficient wake-up schedule during power mode transition considering spurious glitches phenomenon","author":"chen","year":"2007","journal-title":"Proc Int Conf Comput -Aided Des (ICCAD)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821546"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.891093"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1145\/1278480.1278502","article-title":"fine-grained sleep transistor sizing algorithm for leakage power minimization","author":"de-shiuan chiou","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493907"},{"key":"ref22","first-page":"1","article-title":"sleep transistor design and implementationsimple concepts yet challenges to be optimum","author":"shi","year":"2006","journal-title":"Proc VLSI-DAT"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MELCON.2006.1653038"},{"key":"ref23","author":"uyemura","year":"2002","journal-title":"Introduction to VLSI Circuits and Systems"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5393244\/05109471.pdf?arnumber=5109471","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:40Z","timestamp":1633910380000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5109471\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":23,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2010324","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,2]]}}}