{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T02:54:06Z","timestamp":1779245646326,"version":"3.51.4"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2010,3,1]],"date-time":"2010-03-01T00:00:00Z","timestamp":1267401600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/tvlsi.2008.2010830","type":"journal-article","created":{"date-parts":[[2009,4,15]],"date-time":"2009-04-15T16:02:43Z","timestamp":1239811363000},"page":"378-391","source":"Crossref","is-referenced-by-count":20,"title":["Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology"],"prefix":"10.1109","volume":"18","author":[{"given":"Arthur","family":"Nieuwoudt","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jamil","family":"Kawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yehia","family":"Massoud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","year":"2006","journal-title":"Raphael NXT Version 2006 12"},{"key":"ref32","year":"2007","journal-title":"StarRCXT Version 2007 06"},{"key":"ref31","year":"2007","journal-title":"PrimeTime SI Version 2007 06"},{"key":"ref30","year":"2007","journal-title":"Astro Version 2007 03"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776068"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.825480"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"294","DOI":"10.1109\/MICRO.2002.1176258","article-title":"orion: a power-performance simulator for interconnection networks","author":"wang","year":"2002","journal-title":"Proc IEEE\/ACM Int Sym Microarchitect"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.8"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357783"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233639"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.72"},{"key":"ref14","first-page":"135","article-title":"performance-aware cmp fill pattern optimization","author":"kahng","year":"2007","journal-title":"Proc Int VLSI Multilevel Interconnection Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/16.661228"},{"key":"ref16","first-page":"485","article-title":"efficient capacitance extraction method for interconnects with dummy fills","author":"kurokawa","year":"2004","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.47"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.126"},{"key":"ref19","first-page":"31 3 1","article-title":"analyzing the effects of floating dummy-fills: from feature scale analysis to full-chip rc extraction","author":"lee","year":"2001","journal-title":"Proc IEEE Int Electron Dev Meeting"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842798"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196111"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2000.855281"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.915378"},{"key":"ref6","first-page":"3","article-title":"dummy fill density analysis with coupling constraints","author":"xiang","year":"2007","journal-title":"Proc Int Symp Phys Des"},{"key":"ref29","first-page":"954","article-title":"pessimism reduction in crosstalk noise aware sta","author":"becer","year":"2005","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907061"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.931037"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775841"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320844"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.974138"},{"key":"ref1","first-page":"55","article-title":"troy: track router with yield-driven wire planning","author":"cho","year":"2007","journal-title":"Proc IEEE\/ACM Des Autom Conf"},{"key":"ref20","first-page":"373","article-title":"investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling","author":"lee","year":"2003","journal-title":"Proc Int Symp Qual Electron Des"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.11"},{"key":"ref21","first-page":"456","article-title":"simple and accurate models for capacitance increment due to metal fill insertion","author":"kim","year":"2007","journal-title":"Proc Asia South Pacific Des Autom Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560053"},{"key":"ref23","author":"chiang","year":"2007","journal-title":"Design for Manufacturability and Yield for Nanoscale CMOS"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810800"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2001.930082"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5419135\/04814466.pdf?arnumber=4814466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:44Z","timestamp":1633910384000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4814466\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":37,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2010830","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,3]]}}}