{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,23]],"date-time":"2025-10-23T05:22:25Z","timestamp":1761196945734},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2009,7,1]],"date-time":"2009-07-01T00:00:00Z","timestamp":1246406400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,7]]},"DOI":"10.1109\/tvlsi.2008.2012054","type":"journal-article","created":{"date-parts":[[2009,6,10]],"date-time":"2009-06-10T14:31:44Z","timestamp":1244644304000},"page":"883-892","source":"Crossref","is-referenced-by-count":16,"title":["Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic"],"prefix":"10.1109","volume":"17","author":[{"family":"Tsung-Te Liu","sequence":"first","affiliation":[]},{"given":"L.P.","family":"Alarcon","sequence":"additional","affiliation":[]},{"given":"M.D.","family":"Pierson","sequence":"additional","affiliation":[]},{"given":"J.M.","family":"Rabaey","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243769"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2001.945400"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824307"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1007\/BF02108187","article-title":"performance of iterative computation in self-timed rings","volume":"7","author":"williams","year":"1994","journal-title":"J VLSI Signal Process"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2012054"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2007.136"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801606"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234195"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5089930\/05067009.pdf?arnumber=5067009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:00:23Z","timestamp":1633910423000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5067009\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7]]},"references-count":11,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2012054","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,7]]}}}