{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T20:15:56Z","timestamp":1694636156322},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2009,7,1]],"date-time":"2009-07-01T00:00:00Z","timestamp":1246406400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2009,7]]},"DOI":"10.1109\/tvlsi.2008.2012156","type":"journal-article","created":{"date-parts":[[2009,6,25]],"date-time":"2009-06-25T13:53:34Z","timestamp":1245938014000},"page":"855-868","source":"Crossref","is-referenced-by-count":6,"title":["Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings"],"prefix":"10.1109","volume":"17","author":[{"given":"Victor","family":"Khomenko","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"crossref","first-page":"309","DOI":"10.1007\/3-540-65306-6_19","volume":"1491","author":"silva","year":"1998","journal-title":"Lectures on Petri Nets I Basic Models"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/CSD.2001.981773"},{"key":"ref30","first-page":"448","article-title":"a general state graph transformation framework for asynchronous synthesis","author":"lin","year":"1994","journal-title":"Proc EURO-DAC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014746130920"},{"key":"ref11","author":"khomenko","year":"2003","journal-title":"Model checking based on prefixes of Petri net unfoldings"},{"key":"ref12","first-page":"164","article-title":"using unfoldings to avoid state explosion problem in the verification of asynchronous circuits","volume":"663","author":"mcmillan","year":"1992","journal-title":"Proc CAV"},{"key":"ref13","author":"semenov","year":"1997","journal-title":"Verification and synthesis of asynchronous control circuits using petri net unfoldings"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CSD.2003.1207699"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CSD.2004.1309112"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253724"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73094-1_14"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2007.48"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2007.48"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2006.21"},{"key":"ref4","first-page":"199","article-title":"signal graphs: from self-timed to timed ones","author":"rosenblum","year":"1985","journal-title":"Proc Int Workshop Timed Petri Nets"},{"key":"ref27","author":"carmona","year":"2006","journal-title":"private communication"},{"key":"ref3","author":"chu","year":"1987","journal-title":"Synthesis of self-timed VLSI circuits from graph-theoretic specifications"},{"key":"ref6","volume":"5","author":"van berkel","year":"1993","journal-title":"Cambridge International Series on Parallel Computation"},{"key":"ref29","first-page":"86","article-title":"automatic handshake expansion and reshuffling using concurrency reduction","author":"cortadella","year":"1998","journal-title":"Proc HWPN"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/45.1.12"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.859516"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907238"},{"key":"ref2","year":"2007","journal-title":"International Technology Roadmap for Semiconductors Design"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-55989-1","author":"cortadella","year":"2002","journal-title":"Logic Synthesis of Asynchronous Controllers and Interfaces"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73094-1_15"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611972863.9"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1","DOI":"10.3233\/SAT190014","article-title":"translating pseudo-boolean constraints into sat","volume":"2","author":"en","year":"2006","journal-title":"J Satisfiability Boolean Model Comput"},{"key":"ref21","author":"wegener","year":"1987","journal-title":"The Complexity of Boolean Functions"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129875"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1137\/0203011"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/5.24143"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2006.17"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5089930\/05089937.pdf?arnumber=5089937","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:58Z","timestamp":1633910398000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5089937\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,7]]},"references-count":32,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2012156","relation":{},"ISSN":["1063-8210"],"issn-type":[{"value":"1063-8210","type":"print"}],"subject":[],"published":{"date-parts":[[2009,7]]}}}