{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T12:52:33Z","timestamp":1762865553553},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2010,4,1]],"date-time":"2010-04-01T00:00:00Z","timestamp":1270080000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,4]]},"DOI":"10.1109\/tvlsi.2009.2013231","type":"journal-article","created":{"date-parts":[[2009,7,22]],"date-time":"2009-07-22T14:58:31Z","timestamp":1248274711000},"page":"541-552","source":"Crossref","is-referenced-by-count":53,"title":["Single- and Multi-core Configurable AES Architectures for Flexible Security"],"prefix":"10.1109","volume":"18","author":[{"given":"Mao-Yin","family":"Wang","sequence":"first","affiliation":[]},{"given":"Chih-Pin","family":"Su","sequence":"additional","affiliation":[]},{"given":"Chia-Lung","family":"Horng","sequence":"additional","affiliation":[]},{"given":"Cheng-Wen","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Chih-Tsun","family":"Huang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","article-title":"the implementations of the reconfigurable rijndael algorithm with throughput of 4.9 gbps","author":"yen","year":"2005","journal-title":"Proc 18th VLSI Des \/CAD Symp"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2006.02.018"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/12.508323"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010996"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/APASIC.2002.1031539"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/SISW.2003.10004"},{"key":"ref10","author":"hennessy","year":"1996","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234240"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360309"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/611847.611848"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339512"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"296","DOI":"10.1109\/ASAP.2002.1030728","article-title":"a novel pipelined threads architecture for aes encryption algorithm","author":"alam","year":"2002","journal-title":"Proc IEEE Int Conf Appl -Specific Syst Architectures Process"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303101"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2004.1413016"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44709-1_8"},{"key":"ref19","first-page":"162","article-title":"jbits implementations of the advanced encryption standard (rijndael)","volume":"2147","author":"mcmillan","year":"2001","journal-title":"Proc 11th Int Conf FPL Appl"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2003.1252803"},{"key":"ref4","year":"2003","journal-title":"Intel IXP2850 Network Processor Product Brief"},{"key":"ref27","author":"satoh","year":"2003","journal-title":"Cryptographic Hardware and Embedded Sys 2003"},{"key":"ref3","author":"stanley","year":"2003","journal-title":"Security processors"},{"key":"ref6","year":"1999","journal-title":"Data Encryption Standard (DES)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466189"},{"key":"ref5","year":"2001","journal-title":"Advanced Encryption Standard (AES)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.17487\/rfc3602"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.17487\/rfc3268"},{"key":"ref2","author":"frier","year":"1996","journal-title":"The SSL protocol version 3 0"},{"key":"ref9","year":"2004","journal-title":"IEEE 802 11i Standard"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.17487\/rfc2401"},{"key":"ref20","first-page":"220","article-title":"experimental testing of the gigabit ipsec-compliant implementations of rijndael and triple des using slaac-1v fpga accelerator board","volume":"2200","author":"chodowiec","year":"2001","journal-title":"Proc ISCAS"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106754"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44709-1_6"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45682-1_15"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.808300"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1190589"},{"key":"ref25","first-page":"67","volume":"2271","author":"wolkerstorfer","year":"2002","journal-title":"CT-RSA 2002"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5437466\/05169969.pdf?arnumber=5169969","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:00Z","timestamp":1633913040000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5169969\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2013231","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,4]]}}}