{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,9]],"date-time":"2026-03-09T17:39:26Z","timestamp":1773077966510,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2010,4,1]],"date-time":"2010-04-01T00:00:00Z","timestamp":1270080000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,4]]},"DOI":"10.1109\/tvlsi.2009.2014772","type":"journal-article","created":{"date-parts":[[2009,11,23]],"date-time":"2009-11-23T20:32:57Z","timestamp":1259008377000},"page":"679-684","source":"Crossref","is-referenced-by-count":9,"title":["Accurate Predictive Interconnect Modeling for System-Level Design"],"prefix":"10.1109","volume":"18","author":[{"given":"Luca P.","family":"Carloni","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swamy V.","family":"Muddu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alessandro","family":"Pinto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kambiz","family":"Samadi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Puneet","family":"Sharma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569710"},{"key":"ref32","first-page":"503","article-title":"wire sizing and shaping with scattering effect for nanoscale interconnection","author":"shi","year":"2006","journal-title":"Proc IEEE ASPDAC"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/640006.640010"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/43.285250"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/43.828553"},{"key":"ref10","author":"de micheli","year":"2006","journal-title":"Networks on Chip"},{"key":"ref11","first-page":"166","article-title":"network on chip: an architecture for billion transistor era","author":"hemani","year":"2000","journal-title":"Proc 17th IEEE NORCHIP Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195549"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/b105353"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref15","year":"2007","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref16","year":"2004","journal-title":"LEF\/DEF Language Reference"},{"key":"ref17","year":"2004","journal-title":"Liberty File Format Liberty NCX User Guide"},{"key":"ref18","year":"2008","journal-title":"Star-RCXT User s Guide"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/43.712097"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2006.10.048"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405680"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483952"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5433-2"},{"key":"ref5","first-page":"56","article-title":"effects of global interconnect optimizations on performance estimation of deep submicron design","author":"cao","year":"2000","journal-title":"Proc IEEE ICCAD"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.759720"},{"key":"ref2","author":"bakoglu","year":"1990","journal-title":"Circuits Interconnections and Packaging for VLSI"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.506141"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628872"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810800"},{"key":"ref22","author":"pinto","year":"2007","journal-title":"A methodology and an open software infrastructure for constraint-driven synthesis of on-chip communications"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.45867"},{"key":"ref24","year":"2008","journal-title":"Predictive Technology Model"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.138"},{"key":"ref26","year":"2005","journal-title":"BSIM Model"},{"key":"ref25","year":"2004","journal-title":"PrimeTime User Guide"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5437466\/05337968.pdf?arnumber=5337968","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:27Z","timestamp":1633913127000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5337968\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4]]},"references-count":34,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2014772","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,4]]}}}