{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T20:24:09Z","timestamp":1694636649409},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2010,5,1]],"date-time":"2010-05-01T00:00:00Z","timestamp":1272672000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/tvlsi.2009.2015324","type":"journal-article","created":{"date-parts":[[2009,5,27]],"date-time":"2009-05-27T15:37:54Z","timestamp":1243438674000},"page":"831-835","source":"Crossref","is-referenced-by-count":0,"title":["Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC\/H.264 Video Compression"],"prefix":"10.1109","volume":"18","author":[{"given":"Asral","family":"Bahari","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tughrul","family":"Arslan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmet T.","family":"Erdogan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1996.497616"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSS.1998.730611"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.93"},{"key":"ref6","first-page":"29","article-title":"power optimization of system-level address buses based on software profiling","author":"fornaciari","year":"2000","journal-title":"Proc 7th Int Workshop Hardw \/Softw Co-Design (CODES)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/92.766748"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1997.580414"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/GLSV.1999.757458"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2004.1277880"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.863637"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/30.536150"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5453312\/04957021.pdf?arnumber=4957021","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:13Z","timestamp":1633913053000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4957021\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":11,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2015324","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,5]]}}}