{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T14:25:53Z","timestamp":1785248753342,"version":"3.55.0"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2010,5,1]],"date-time":"2010-05-01T00:00:00Z","timestamp":1272672000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/tvlsi.2009.2015666","type":"journal-article","created":{"date-parts":[[2009,7,22]],"date-time":"2009-07-22T14:58:31Z","timestamp":1248274711000},"page":"843-847","source":"Crossref","is-referenced-by-count":75,"title":["VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory"],"prefix":"10.1109","volume":"18","author":[{"given":"Hyojin","family":"Choi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wonyong","family":"Sung","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.568829"},{"key":"ref3","first-page":"248","article-title":"low-power high-throughput bch error correction vlsi design for multi-level cell <emphasis emphasistype=\"smcaps\">nand<\/emphasis> flash memories","author":"liu","year":"2006","journal-title":"Proc Int Workshop SiPS"},{"key":"ref10","first-page":"517","article-title":"ultra folded high-speed architectures for reedsolomon decoders","author":"seth","year":"2006","journal-title":"Proc Int Conf VLSI Des"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.823655"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IWVDVT.2005.1504560"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/92.953498"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.850125"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811709"},{"key":"ref9","first-page":"73v","article-title":"area efficient parallel decoder architecture for long bch codes","author":"chen","year":"2004","journal-title":"Proc IEEE Int Conf Acoust Speech Signal Process"},{"key":"ref1","author":"lin","year":"1983","journal-title":"Error Control Coding"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5453312\/05169834.pdf?arnumber=5169834","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:16Z","timestamp":1633913056000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5169834\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":10,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2015666","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,5]]}}}