{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,12]],"date-time":"2026-05-12T02:32:18Z","timestamp":1778553138593,"version":"3.51.4"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2010,5,1]],"date-time":"2010-05-01T00:00:00Z","timestamp":1272672000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/tvlsi.2009.2017912","type":"journal-article","created":{"date-parts":[[2009,8,7]],"date-time":"2009-08-07T15:01:34Z","timestamp":1249657294000},"page":"750-762","source":"Crossref","is-referenced-by-count":25,"title":["A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors"],"prefix":"10.1109","volume":"18","author":[{"given":"Zhiyi","family":"Yu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bevan M.","family":"Baas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017912"},{"key":"ref11","author":"chapiro","year":"1984","journal-title":"Globally-Asynchronous Locally-Synchronous Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/71.127260"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882474"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1987.1096719"},{"key":"ref16","first-page":"428","article-title":"an asynchronous array of simple processors for dsp applications","author":"yu","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183551"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.903938"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001947"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"ref27","first-page":"378","article-title":"performance and power analysis of glabally asynchronous locally synchronous multi-processor systems","author":"yu","year":"2006","journal-title":"Proc IEEE Computer Soc Annu Symp VLSI (ISVLSI)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916616"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863753"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.29"},{"key":"ref8","first-page":"2","article-title":"interconnect architecture exploration for low-energy reconfigurable single-chip dsps","author":"zhang","year":"1999","journal-title":"Proc IEEE Comput Soc Workshop VLSI"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234252"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464952"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234253"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585936"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373392"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.16"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/4.881217"},{"key":"ref26","first-page":"174","article-title":"implementing tile-based chip multiprocessors with gals clocking styles","author":"yu","year":"2006","journal-title":"Proc ICCD"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243842"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5453312\/05191030.pdf?arnumber=5191030","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:04:51Z","timestamp":1633910691000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5191030\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":29,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2017912","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,5]]}}}