{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T00:08:55Z","timestamp":1705018135740},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2010,8,1]],"date-time":"2010-08-01T00:00:00Z","timestamp":1280620800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,8]]},"DOI":"10.1109\/tvlsi.2009.2021478","type":"journal-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T18:47:26Z","timestamp":1255459646000},"page":"1173-1184","source":"Crossref","is-referenced-by-count":5,"title":["Variation-Aware System-Level Power Analysis"],"prefix":"10.1109","volume":"18","author":[{"given":"Saumya","family":"Chandra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kanishka","family":"Lahiri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anand","family":"Raghunathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sujit","family":"Dey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","year":"0","journal-title":"ARM946E-S - ARM Processor"},{"key":"ref11","year":"0","journal-title":"AMBA 2 0 Specification"},{"key":"ref12","year":"0","journal-title":"Cell Based 1C CB-90 L\/M\/H Type Features\/Basic Specifications NEC Electronics"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.138"},{"key":"ref14","year":"0","journal-title":"UC Santa Cruz Floor-Planning Tool"},{"key":"ref15","year":"0","journal-title":"HotSpot 3 0 Temperature Modeling Tool"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871529"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850860"},{"key":"ref18","year":"0","journal-title":"BACPACBerkeley advanced chip performance calculator"},{"key":"ref19","year":"0","journal-title":"The open systemC initiative"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.86"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065716"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859480"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065717"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370363"},{"key":"ref7","first-page":"262","article-title":"process variation aware cache leakage management","author":"meng","year":"2006","journal-title":"Proc ISLPED"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996693"},{"key":"ref1","first-page":"19","article-title":"full-chip subthreshold leakage power prediction model for sub-0.18 urn cmos","author":"narendra","year":"2002","journal-title":"Proc ISLPED"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231840"},{"key":"ref20","year":"0","journal-title":"BPTMBerkeley predictive technology models"},{"key":"ref22","first-page":"342","article-title":"considering process variations during system-level power analysis","author":"chandra","year":"2006","journal-title":"Proc ISLPED"},{"key":"ref21","year":"0","journal-title":"MATLABHigh-Level Technical Computing Environment"},{"key":"ref23","year":"0","journal-title":"Industry Standard Deep Submicron SPICE MOS Device Model for Circuit Designs"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5518454\/05286250.pdf?arnumber=5286250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:04Z","timestamp":1633909924000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5286250\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,8]]},"references-count":23,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2021478","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,8]]}}}