{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:46:42Z","timestamp":1759146402306},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/tvlsi.2009.2022269","type":"journal-article","created":{"date-parts":[[2009,9,4]],"date-time":"2009-09-04T14:38:22Z","timestamp":1252075102000},"page":"1287-1300","source":"Crossref","is-referenced-by-count":5,"title":["Control for Power Gating of Wires"],"prefix":"10.1109","volume":"18","author":[{"given":"Kris","family":"Heyrman","sequence":"first","affiliation":[]},{"given":"Antonis","family":"Papanikolaou","sequence":"additional","affiliation":[]},{"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[]},{"given":"Peter","family":"Veelaert","sequence":"additional","affiliation":[]},{"given":"Wilfried","family":"Philips","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2004.1337695"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219148"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/b101914"},{"key":"ref30","author":"papanikolaou","year":"0","journal-title":"Application-driven software configuration of communication networks and memory organizations"},{"key":"ref35","first-page":"110","article-title":"interconnect-aware high-level synthesis for low power","author":"lin","year":"2002","journal-title":"Proc IEEE\/ACM Int Conf Comp Aided Design (ICCAD 2002)"},{"key":"ref34","first-page":"2","article-title":"interconnect architecture exploration for low-energy reconfigurable single-chip dsps","author":"zhang","year":"1999","journal-title":"Proc IEEE Computer Society Workshop on VLSI (VLSI 99)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICTEL.2003.1191583"},{"key":"ref11","author":"grover","year":"2004","journal-title":"Mesh-Based Survivable Networks Options and Strategies for Optical MPLS SONET and ATM Networking"},{"key":"ref12","year":"0","journal-title":"DLX Simulator in SystemC"},{"key":"ref13","year":"0","journal-title":"Gsm 06 10 Lossy Speech Compression"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357982"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.900758"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373575"},{"key":"ref17","author":"hennessy","year":"1995","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref18","first-page":"52","article-title":"energy consumption for transport of control information on a segmented software-controlled communication architecture","volume":"3985","author":"heyrman","year":"2006","journal-title":"2nd Int Workshop Appl Reconfig Computing (ARC 2006)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2007.4427432"},{"key":"ref28","article-title":"low-power arithmetics for soc","author":"noll","year":"0","journal-title":"Int Symp System-on-Chip (SOC 2007)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.804706"},{"key":"ref27","year":"0","journal-title":"Magma Blast Fusion"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.748197"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICNICONSMCL.2006.169"},{"key":"ref5","year":"0","journal-title":"CACTI"},{"key":"ref8","author":"duato","year":"2002","journal-title":"Interconnection Networks An Engineering Approach"},{"key":"ref7","author":"dally","year":"2004","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref2","year":"0","journal-title":"The ATOMIUM Tool Suite"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.7155\/jgaa.00064"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2005.845037"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/606603.606606"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828127"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/4.50295"},{"key":"ref26","first-page":"176","article-title":"low-energy encoding for deep-submicron address buses","author":"macchiarulo","year":"2002","journal-title":"Proc ISLPED 2001"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/SSST.1996.493540"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5556483\/05229122.pdf?arnumber=5229122","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:51Z","timestamp":1633909911000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5229122\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":35,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2022269","relation":{},"ISSN":["1063-8210"],"issn-type":[{"value":"1063-8210","type":"print"}],"subject":[],"published":{"date-parts":[[2010,9]]}}}