{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:34:53Z","timestamp":1781886893318,"version":"3.54.5"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/tvlsi.2009.2026048","type":"journal-article","created":{"date-parts":[[2009,9,24]],"date-time":"2009-09-24T19:51:15Z","timestamp":1253821875000},"page":"1660-1671","source":"Crossref","is-referenced-by-count":17,"title":["SRAM Leakage Reduction by Row\/Column Redundancy Under Random Within-Die Delay Variation"],"prefix":"10.1109","volume":"18","author":[{"given":"Maziar","family":"Goudarzi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tohru","family":"Ishihara","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref32","year":"2009","journal-title":"The Fujitsu Analog and RF CMOS Technology"},{"key":"ref31","doi-asserted-by":"crossref","DOI":"10.1080\/10691898.2008.11889560","article-title":"central limit theorem: new socr applet and demonstration activity","volume":"16","author":"dinov","year":"2008","journal-title":"J Statist Educ"},{"key":"ref30","year":"2009","journal-title":"CACTI an integrated cache access time cycle time area leakage and dynamic power model"},{"key":"ref10","first-page":"15","article-title":"yield-aware cache architectures","author":"ozdemir","year":"2006","journal-title":"Proc Int Symp Microarchitecture (Micro)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2006.4271847"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"ref14","first-page":"148","article-title":"drowsy caches: simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"Proc Int Symp Comput Arch (ISCA)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393947"},{"key":"ref16","first-page":"46","article-title":"opportunities in future physical implementation and manufacturing handoff flows","author":"kahng","year":"2007","journal-title":"Proc Int SoC Des Conf (ISOCC)"},{"key":"ref17","doi-asserted-by":"crossref","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-vdd: a circuit technique to reduce leakage in cache memories","author":"powell","year":"2000","journal-title":"Proc Int Symp Low Power Electron Des (ISLPED)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358058"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/0-306-48139-1_13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.58"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270300"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743312"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"710","DOI":"10.1145\/74382.74510","article-title":"on the repair of redundant rams","author":"hemmady","year":"1989","journal-title":"26th ACM\/IEEE Design Automation Conference"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766701"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892185"},{"key":"ref2","year":"2007","journal-title":"International Technology Roadmap for SemiconductorsDesign"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560207"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2006.4271802"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000459"},{"key":"ref22","first-page":"87","article-title":"sram methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes","author":"kanj","year":"2008","journal-title":"Proc Int Symp Low Power Electron Des (ISLPED)"},{"key":"ref21","first-page":"174","article-title":"abnormal leakage suppression (als) scheme for low standby current srams","author":"kanda","year":"2001","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref24","author":"weste","year":"2005","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref23","year":"2009","journal-title":"Predictive Technology Model"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908004"},{"key":"ref25","author":"keeth","year":"2001","journal-title":"DRAM Circuit Design A Tutorial"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5634429\/05256337.pdf?arnumber=5256337","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:10Z","timestamp":1633910350000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5256337\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":32,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2026048","relation":{},"ISSN":["1063-8210"],"issn-type":[{"value":"1063-8210","type":"print"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}