{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:11:11Z","timestamp":1758892271532},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2011,2,1]],"date-time":"2011-02-01T00:00:00Z","timestamp":1296518400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/tvlsi.2009.2029232","type":"journal-article","created":{"date-parts":[[2009,11,3]],"date-time":"2009-11-03T15:14:52Z","timestamp":1257261292000},"page":"283-294","source":"Crossref","is-referenced-by-count":11,"title":["The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources"],"prefix":"10.1109","volume":"19","author":[{"given":"Phoebe Ping","family":"Chen","sequence":"first","affiliation":[]},{"given":"Andy","family":"Ye","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"koren","year":"2002","journal-title":"Computer Arithmetic Algorithms"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1990.124841"},{"key":"ref13","first-page":"215","article-title":"a detailed router for allocating wire segments in field-programmable gate arrays","author":"lemieux","year":"1993","journal-title":"Proc ACM\/SIGDA Physical Design Workshop"},{"key":"ref14","year":"1994","journal-title":"The Programmable Logic Data Book"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/267665.267682"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/225871.225886"},{"key":"ref17","author":"wilton","year":"1997","journal-title":"Architectures and algorithms for field-programmable gate arrays with embedded memory"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"274","DOI":"10.1007\/978-3-540-48302-1_28","article-title":"a new switch block for segmented fpgas","author":"masud","year":"1999","journal-title":"Proc IEEE Int Conf Field Programmable Logic Applications"},{"key":"ref19","first-page":"122","article-title":"analytical framework for switch block design","author":"lemieux","year":"2002","journal-title":"Proc IEEE Int Conf Field Programmable Logic Applications"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296428"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296444"},{"key":"ref27","author":"chen","year":"2008","journal-title":"The effect of multi-bit correlation on the design of routing resources in field programmable gate arrays"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903407"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876095"},{"key":"ref7","first-page":"195","article-title":"an fpga architecture with enhanced datapath functionality","author":"leijten-nowak","year":"2003","journal-title":"Proc ACM\/SIGDA Int Symp Field Programmable Gate Arrays"},{"key":"ref2","first-page":"126","article-title":"RaPiD&#x2014;Reconfigurable pipelined datapath","author":"ebeling","year":"1996","journal-title":"Proc Int Workshop Field-Programmable Logic Applications"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050178"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1155\/1996\/95942"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2002.1188685"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/54.655177"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393260"},{"key":"ref24","author":"ye","year":"2004","journal-title":"Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits"},{"key":"ref23","year":"1999","journal-title":"Pico-Java Processor Design Documentation"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/92.475966"},{"key":"ref25","first-page":"213","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"Proc Intl Conf Field Programmable Logic and Appl"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5695105\/05291700.pdf?arnumber=5291700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:25Z","timestamp":1633910365000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5291700\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":28,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2029232","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,2]]}}}