{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T18:57:16Z","timestamp":1761418636307},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/tvlsi.2009.2031290","type":"journal-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T18:47:26Z","timestamp":1255459646000},"page":"166-170","source":"Crossref","is-referenced-by-count":5,"title":["Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise"],"prefix":"10.1109","volume":"18","author":[{"given":"Harmander","family":"Singh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rahul","family":"Rao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kanak","family":"Agarwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dennis","family":"Sylvester","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Richard","family":"Brown","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687996"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775881"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2003.1257135"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878290"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231847"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010631"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050029"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"ref18","first-page":"779","article-title":"Leakage-and crosstalk-aware bus encoding for total power reduction","author":"deogun","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349334"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300073"},{"key":"ref3","first-page":"141","article-title":"subthreshold leakage and modeling techniques","author":"kao","year":"2002","journal-title":"Proc Int Conf Comput -Aided Des"},{"key":"ref6","author":"cheng","year":"2000","journal-title":"Interconnect Analysis and Synthesis"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/82.673643"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781357"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968598"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159681"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606670"},{"key":"ref20","first-page":"554","article-title":"inductance: implications and solutions for high-speed digital circuitson-chip signaling","volume":"2","author":"morton","year":"2002","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"ref21","first-page":"199","article-title":"simultaneous shield insertion and net ordering under explicit rlc noise constraint","author":"lepak","year":"2001","journal-title":"Proc Des Autom Conf"},{"key":"ref24","first-page":"661","article-title":"high performance and low power transistors integrated in 65 nm bulk cmos technology","author":"luo","year":"2004","journal-title":"Proc Int Electron Devices Meet"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5357587\/05286228.pdf?arnumber=5286228","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:20Z","timestamp":1633909940000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5286228\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":24,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2031290","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,1]]}}}