{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:12:38Z","timestamp":1763467958668},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2011,2,1]],"date-time":"2011-02-01T00:00:00Z","timestamp":1296518400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/tvlsi.2009.2032916","type":"journal-article","created":{"date-parts":[[2009,11,3]],"date-time":"2009-11-03T15:14:52Z","timestamp":1257261292000},"page":"250-263","source":"Crossref","is-referenced-by-count":21,"title":["Energy-Efficient Hardware Data Prefetching"],"prefix":"10.1109","volume":"19","author":[{"given":"Yao","family":"Guo","sequence":"first","affiliation":[]},{"given":"Pritish","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"Mahmoud Abdullah","family":"Bennaser","sequence":"additional","affiliation":[]},{"given":"Saurabh","family":"Chheda","sequence":"additional","affiliation":[]},{"given":"Csaba Andras","family":"Moritz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903254"},{"key":"ref38","first-page":"388","article-title":"guided region prefetching: a cooperative hardware\/software approach","author":"wang","year":"2003","journal-title":"Proc ISCA"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514217"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301645"},{"key":"ref31","first-page":"339","article-title":"pare: a power-aware hardware data prefetching engine","author":"guo","year":"2005","journal-title":"Proc ISLPED"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28641-7_1"},{"key":"ref37","author":"srinivasan","year":"1999","journal-title":"A static filter for reducing prefetch traffic"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781161"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/512553.512554"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/512529.512555"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/143365.143488"},{"key":"ref40","article-title":"introduction to multi-core","author":"ganesan","year":"2007","journal-title":"Intel-FAER Series Lectures Comput Arch"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-72685-2_20"},{"key":"ref12","first-page":"19","article-title":"compiler techinques for data prefetching on the powerpc","author":"bernstein","year":"1995","journal-title":"Proc PACT"},{"key":"ref13","first-page":"25","article-title":"design of the hp pa 7200 cpu","volume":"47","author":"chan","year":"1996","journal-title":"Hewlett-Packard J"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953306"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"ref16","article-title":"data prefetching on the hp pa8000","author":"santhanam","year":"1997","journal-title":"Proc ISCA-24"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"726","DOI":"10.1145\/277044.277226","article-title":"Power considerations in the design of the Alpha 21264 microprocessor","author":"gowan","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref18","first-page":"49","article-title":"a 160-mhz, 32-b, 0.5-w cmos risc microprocessor","volume":"9","author":"montanaro","year":"1997","journal-title":"Digital Tech J Digital Equipment Corp"},{"key":"ref19","author":"burger","year":"1997","journal-title":"The SimpleScalar tool set version 2 0"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566422"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765944"},{"key":"ref27","first-page":"133","article-title":"cool-mem: combining statically speculative memory accessing with selective address translation for energy efficiency","author":"ashok","year":"2002","journal-title":"Proc ASPLOS-X"},{"key":"ref3","first-page":"115","article-title":"dependence based prefetching for linked data structures","author":"roth","year":"1998","journal-title":"Proc ASPLOS V"},{"key":"ref6","author":"mowry","year":"1994","journal-title":"\"Tolerating Latency Through Software Controlled Data Prefetching \""},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/11574859_6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605427"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237190"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476830"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"ref9","first-page":"133","article-title":"memory-system design considerations for dynamically-scheduled processors","author":"farkas","year":"1997","journal-title":"Proc ISCA-24"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1978.218016"},{"key":"ref20","author":"wilson","year":"1994","journal-title":"SUIF A parallelizing and optimizing research compiler"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"ref21","first-page":"518","article-title":"energy characterization of hardware-based data prefetching","author":"guo","year":"2004","journal-title":"Proc Int Conf Comput Des (ICCD)"},{"key":"ref24","year":"2000","journal-title":"The Standard Performance Evaluation Corporation"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/201059.201065"},{"key":"ref26","article-title":"highly-associative caches for low-power processors","author":"zhang","year":"2000","journal-title":"Kool Chips Workshop MICRO-33"},{"key":"ref25","article-title":"a step-by-step design and analysis of low power caches for embedded processors","author":"bennaser","year":"2005","journal-title":"Boston Area Arch Workshop (BARC)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5695105\/05291706.pdf?arnumber=5291706","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:58:43Z","timestamp":1633910323000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5291706\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":40,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2032916","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,2]]}}}