{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,13]],"date-time":"2024-06-13T04:37:20Z","timestamp":1718253440453},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/tvlsi.2009.2034380","type":"journal-article","created":{"date-parts":[[2009,11,30]],"date-time":"2009-11-30T19:57:12Z","timestamp":1259611032000},"page":"1745-1752","source":"Crossref","is-referenced-by-count":17,"title":["A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB\/s Burst Mode"],"prefix":"10.1109","volume":"18","author":[{"given":"Katsuhiko","family":"Hoya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daisaburo","family":"Takashima","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinichiro","family":"Shiratake","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryu","family":"Ogiwara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadashi","family":"Miyakawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hidehiro","family":"Shiga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sumiko M.","family":"Doumae","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sumito","family":"Ohtsuki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoshinori","family":"Kumura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Susumu","family":"Shuto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tohru","family":"Ozaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"Yamakawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Iwao","family":"Kunishima","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akihiro","family":"Nitayama","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuso","family":"Fujii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825241"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837967"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.62132"},{"key":"ref13","first-page":"39","article-title":"empirical model for fatigue of pzt ferroelectric memories","author":"rodriguez","year":"2002","journal-title":"Proc 40th Ann Reliab Phys Symp"},{"key":"ref4","first-page":"272","article-title":"a 0.4-um 3.3-v 1t\/1c 4-mb nonvolatile ferroelectric ram with fixed bit-line reference voltage scheme and data protection","author":"jeon","year":"2000","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1999.797249"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.962293"},{"key":"ref5","first-page":"162","article-title":"a 0.25-um 3.0-v 1t1c 32-mb nonvolatile ferroelectric ram with address transition detector (atd) and current forcing latch sense amplifier (cflsa) scheme","author":"choi","year":"2002","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051481"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818161"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.668994"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1989.48273"},{"key":"ref9","first-page":"134","article-title":"a 64 mb chain feram with quad bl architecture and 200 mb\/s burst mode","author":"hoya","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5634429\/05339093.pdf?arnumber=5339093","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:00:01Z","timestamp":1633914001000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5339093\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":13,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2034380","relation":{},"ISSN":["1063-8210"],"issn-type":[{"value":"1063-8210","type":"print"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}