{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T10:35:23Z","timestamp":1769078123469,"version":"3.49.0"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T00:00:00Z","timestamp":1301616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/tvlsi.2009.2038165","type":"journal-article","created":{"date-parts":[[2010,3,12]],"date-time":"2010-03-12T13:55:32Z","timestamp":1268402132000},"page":"647-658","source":"Crossref","is-referenced-by-count":94,"title":["Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies"],"prefix":"10.1109","volume":"19","author":[{"given":"Nauman H.","family":"Khan","sequence":"first","affiliation":[]},{"given":"Syed M.","family":"Alam","sequence":"additional","affiliation":[]},{"given":"Soha","family":"Hassoun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306579"},{"key":"ref32","year":"2005","journal-title":"Redistributed Chip Packaging (RCP) Technology"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388564"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147128"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609348"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.92"},{"key":"ref12","first-page":"125","article-title":"Wafer-level 3D interconnects via Cu bonding","author":"morrow","year":"2004","journal-title":"Proc Adv Metallization Conf"},{"key":"ref13","article-title":"Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology","author":"rousseau","year":"2008","journal-title":"Proc IMAPS Device Packag Conf"},{"key":"ref14","year":"2006","journal-title":"Method of forming a through-substrate via"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645754"},{"key":"ref16","first-page":"1946","article-title":"High RF performance TSV silicon carrier for high frequency application","author":"ho","year":"2008","journal-title":"Proc Electron Components Technol Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/POLYTR.2007.4339157"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320826"},{"key":"ref19","author":"wu","year":"2006","journal-title":"Through-substrate interconnects for 3-D integration and RF systems"},{"key":"ref28","year":"2005","journal-title":"Predictive Technology Model (PTM)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364663"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2006.1648688"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870069"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379023"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466143"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233666"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4549941"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/92.974905"},{"key":"ref9","year":"2006","journal-title":"MITLL Low-Power FDSOI CMOS Process Application Notes"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCISE.2003.1166548"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393940"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2007.4387161"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397340"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243773"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"458","DOI":"10.1145\/1057661.1057770","article-title":"3D module placement for congestion and power noise reduction","author":"minz","year":"2005","journal-title":"Proc 10th Great Lakes Symp VLSI"},{"key":"ref26","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796477"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5735629\/05428771.pdf?arnumber=5428771","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,24]],"date-time":"2021-10-24T19:24:01Z","timestamp":1635103441000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5428771\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":33,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2038165","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}