{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T20:42:42Z","timestamp":1694637762795},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T00:00:00Z","timestamp":1301616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/tvlsi.2009.2038922","type":"journal-article","created":{"date-parts":[[2010,2,17]],"date-time":"2010-02-17T14:56:35Z","timestamp":1266418595000},"page":"525-537","source":"Crossref","is-referenced-by-count":8,"title":["A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache"],"prefix":"10.1109","volume":"19","author":[{"given":"Jae-Sung","family":"Yoon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chang-Hyo","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donghyun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lee-Sup","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","year":"2000","journal-title":"OpenGL ES 2 0"},{"key":"ref11","year":"1975","journal-title":"Shader model 3 0"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604595"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002459"},{"key":"ref15","first-page":"539","article-title":"A 3D graphics processor with fast 4D vector inner product units and power aware texture cache","author":"yoon","year":"2008","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.210"},{"key":"ref17","year":"1993","journal-title":"Shader Model 3 0 Using Vertex Textures"},{"key":"ref18","year":"1993","journal-title":"FX Composer 2 0"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.30"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001898"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859330"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.905242"},{"key":"ref5","first-page":"278","article-title":"A 52.4 mW 3D graphics processor with 141 Mvertices\/s vertex shader and 3 power domains of dynamic voltage and frequency scaling","author":"nam","year":"2007","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref8","first-page":"579","article-title":"A 186 Mvertices\/s 161 mW floating-point vertex processor for mobile graphics systems","author":"yu","year":"2007","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001911"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2005.1541596"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332730"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.920315"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5735629\/05411955.pdf?arnumber=5411955","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:47:46Z","timestamp":1633913266000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5411955\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":19,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2009.2038922","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}