{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T12:56:31Z","timestamp":1773406591994,"version":"3.50.1"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2011,5,1]],"date-time":"2011-05-01T00:00:00Z","timestamp":1304208000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/tvlsi.2010.2042086","type":"journal-article","created":{"date-parts":[[2010,3,30]],"date-time":"2010-03-30T18:43:14Z","timestamp":1269974594000},"page":"869-882","source":"Crossref","is-referenced-by-count":38,"title":["A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design"],"prefix":"10.1109","volume":"19","author":[{"given":"Rajiv V.","family":"Joshi","sequence":"first","affiliation":[]},{"given":"Rouwaida","family":"Kanj","sequence":"additional","affiliation":[]},{"given":"Vinod","family":"Ramadurai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705289"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146930"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283784"},{"key":"ref4","first-page":"9","article-title":"Wordline &#38; bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65 nm CMOS designs","author":"kellah","year":"2006","journal-title":"Proc VLSI Circuits Symp"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494075"},{"key":"ref6","year":"2001","journal-title":"Provably correct storage arrays"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405674"},{"key":"ref8","year":"2006","journal-title":"Random access memory with stability enhancement and early ready elimination"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2004.1358816"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2004.1356655"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2006.284405"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5755591\/05439971.pdf?arnumber=5439971","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:37:17Z","timestamp":1633916237000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5439971\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":13,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2042086","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,5]]}}}