{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,5]],"date-time":"2026-10-05T12:43:49Z","timestamp":1791204229629,"version":"4.2.0"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2011,5,1]],"date-time":"2011-05-01T00:00:00Z","timestamp":1304208000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/tvlsi.2010.2043271","type":"journal-article","created":{"date-parts":[[2010,3,12]],"date-time":"2010-03-12T13:55:32Z","timestamp":1268402132000},"page":"900-904","source":"Crossref","is-referenced-by-count":61,"title":["A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors"],"prefix":"10.1109","volume":"19","author":[{"given":"Sheng","family":"Lin","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yong-Bin","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fabrizio","family":"Lombardi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.49"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.818928"},{"key":"ref12","year":"2007","journal-title":"Berkeley Predictive Technology Model website"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.10"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2009.5236005"},{"key":"ref15","year":"2009","journal-title":"The MOSIS Service"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.813129"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1070"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271074"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.15"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2004.839154"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/23.659045"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.60"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5755591\/05428788.pdf?arnumber=5428788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:37:19Z","timestamp":1633916239000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5428788\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":15,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2043271","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,5]]}}}