{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,7]],"date-time":"2026-05-07T16:16:29Z","timestamp":1778170589846,"version":"3.51.4"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2011,6,1]],"date-time":"2011-06-01T00:00:00Z","timestamp":1306886400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/tvlsi.2010.2043964","type":"journal-article","created":{"date-parts":[[2010,3,30]],"date-time":"2010-03-30T18:43:14Z","timestamp":1269974594000},"page":"1011-1022","source":"Crossref","is-referenced-by-count":17,"title":["A Dedicated Monitoring Infrastructure for Multicore Processors"],"prefix":"10.1109","volume":"19","author":[{"given":"Jia","family":"Zhao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sailaja","family":"Madduri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramakrishna","family":"Vadlamani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Burleson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Russell","family":"Tessier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2006.300821"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/40.988687"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183526"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378783"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.03.003"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"ref13","first-page":"477","article-title":"Implementation and evaluation of on-chip network architectures","author":"gratz","year":"2007","journal-title":"Proc IEEE Int Conf Comput Des"},{"key":"ref14","first-page":"765","article-title":"Fault-tolerant routing algorithm for meshes without using virtual channels","volume":"14","author":"chen","year":"1998","journal-title":"J Inf Sci Eng"},{"key":"ref15","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proc IEEE Int Symp High-Perform Comput Arch"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541648"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5245"},{"key":"ref18","first-page":"91","article-title":"Dynamic voltage scaling with links for power optimization of interconnection networks","author":"shang","year":"2003","journal-title":"Proc IEEE Int Symp High-Perform Comput Arch"},{"key":"ref19","year":"2004","journal-title":"UMC's 90 nm 1P9M logic\/mixed mode low-K SP-HVT process library"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/19.1.43"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373411"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.915538"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859902"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"ref29","first-page":"398","article-title":"A distributed critical-path timing monitor for a 65 nm high-performance microprocessor","author":"drake","year":"2007","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.78"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090766"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/rd.516.0733"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681583"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.108"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531579"},{"key":"ref20","author":"renau","year":"2004","journal-title":"SESC Simulator"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"ref21","first-page":"625","article-title":"Thermal trends in emerging technologies","author":"link","year":"2006","journal-title":"Proc IEEE Int Symp Quality Electron Des"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885049"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.03.006"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147051"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687459"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5772207\/05439943.pdf?arnumber=5439943","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:01:02Z","timestamp":1633914062000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5439943\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":34,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2043964","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,6]]}}}