{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:11:42Z","timestamp":1773249102546,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2011,7,1]],"date-time":"2011-07-01T00:00:00Z","timestamp":1309478400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,7]]},"DOI":"10.1109\/tvlsi.2010.2047415","type":"journal-article","created":{"date-parts":[[2010,5,21]],"date-time":"2010-05-21T20:57:37Z","timestamp":1274475457000},"page":"1154-1166","source":"Crossref","is-referenced-by-count":16,"title":["Prediction and Comparison of High-Performance On-Chip Global Interconnection"],"prefix":"10.1109","volume":"19","author":[{"given":"Yulei","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiang","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alina","family":"Deutsch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. Ege","family":"Engin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James F.","family":"Buckwalter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Kuan","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2004549"},{"key":"ref32","first-page":"10","article-title":"A wave-pipelined on-chip interconnect structure for networks-on-chips","author":"xu","year":"2003","journal-title":"Proc IEEE Symp High Perform Interconnects"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.916506"},{"key":"ref30","year":"2003","journal-title":"Networks on Chip"},{"key":"ref10","first-page":"66","article-title":"A 4 Gb\/s\/ch 356 fJ\/b 10 mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90 nm CMOS","author":"kim","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572482"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810337"},{"key":"ref13","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time","author":"schinkel","year":"2007","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref14","first-page":"81","article-title":"A predictive transistor model based on ITRS roadmap","author":"uemura","year":"2006","journal-title":"Proc General Conf IEICE"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.813345"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929763"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.825478"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/5.362754"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801574"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.812509"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.139"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/6040.784477"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.828553"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/5.920582"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.935616"},{"key":"ref5","author":"bakoglu","year":"1990","journal-title":"Circuits Interconnections and Packaging for VLSI"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796511"},{"key":"ref7","first-page":"552","article-title":"Equalized interconnects for on-chip networks: Modeling and optimization framework","author":"kim","year":"2007","journal-title":"Proc IEEE Int Conf Comput -Aided Des"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751859"},{"key":"ref1","year":"2007","journal-title":"Semiconductor Industry Association"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.962285"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859880"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077650"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681646"},{"key":"ref23","first-page":"341","author":"biggs","year":"1975","journal-title":"Towards Global Optimization"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.842259"},{"key":"ref25","year":"2006","journal-title":"IBM Electromagnetic Field Solver Suite of Tools"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5929024\/05463287.pdf?arnumber=5463287","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:43:59Z","timestamp":1633913039000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5463287\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,7]]},"references-count":33,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2047415","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,7]]}}}