{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T16:21:21Z","timestamp":1773678081738,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2011,7,1]],"date-time":"2011-07-01T00:00:00Z","timestamp":1309478400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,7]]},"DOI":"10.1109\/tvlsi.2010.2049038","type":"journal-article","created":{"date-parts":[[2010,5,26]],"date-time":"2010-05-26T13:11:50Z","timestamp":1274879510000},"page":"1192-1204","source":"Crossref","is-referenced-by-count":38,"title":["Impacts of NBTI\/PBTI and Contact Resistance on Power-Gated SRAM With High-$\\kappa$ Metal-Gate Devices"],"prefix":"10.1109","volume":"19","author":[{"given":"Hao-I","family":"Yang","sequence":"first","affiliation":[]},{"given":"Wei","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Ching-Te","family":"Chuang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"439","article-title":"Time dependent <ref_formula><tex Notation=\"TeX\">${V}_{\\rm CCMIN}$<\/tex><\/ref_formula> degradation of SRAM fabricated with high-k gate dielectrics","author":"lin","year":"2007","journal-title":"Proc IEEE Int Reliab Phys Symp"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147172"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320885"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346777"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231828"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917506"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373424"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001872"},{"key":"ref18","first-page":"208","article-title":"A high performance 2.4 Mb L1 and L2 cache compatible 45 nm SRAM with yield improvement capabilities","author":"joshi","year":"2008","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007151"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2010573"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893584"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907996"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896317"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034082"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SMICND.2004.1403001"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2006.1705198"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2009.03.016"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5929024\/05464390.pdf?arnumber=5464390","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:38Z","timestamp":1633913138000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5464390\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,7]]},"references-count":18,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2049038","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,7]]}}}