{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:59:44Z","timestamp":1761580784373},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2011,7,1]],"date-time":"2011-07-01T00:00:00Z","timestamp":1309478400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,7]]},"DOI":"10.1109\/tvlsi.2010.2050158","type":"journal-article","created":{"date-parts":[[2010,6,18]],"date-time":"2010-06-18T19:20:02Z","timestamp":1276888802000},"page":"1263-1276","source":"Crossref","is-referenced-by-count":40,"title":["A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems"],"prefix":"10.1109","volume":"19","author":[{"given":"Juan Antonio","family":"Clemente","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Resano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos","family":"Gonzalez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Mozos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.884052"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2003490"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2007.4439251"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1331331.1331338"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.48"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311264"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/503074.503076"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.100"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1391962.1391966"},{"key":"ref4","first-page":"191","article-title":"Reducing the reconfiguration overhead: A survey of techniques","author":"prez-ramo","year":"2007","journal-title":"Proc Int Conf Eng Reconfig Syst Algorithms (ERSA)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.886411"},{"key":"ref6","first-page":"1","article-title":"A parallel configuration model for reducing the run-time reconfiguration overhead","author":"qu","year":"2006","journal-title":"Proc Des Autom Test Eur (DATE)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253622"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1465","DOI":"10.1109\/TVLSI.2008.2000974","article-title":"Hardware supported task scheduling on dynamically reconfigurable SoC architectures","volume":"16","author":"pan","year":"2008","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993404"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/sj.52.0078"},{"key":"ref1","first-page":"795","article-title":"Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs","author":"marescaux","year":"2002","journal-title":"Proc Int Conf Field Program Logic Appl (FPL)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912097"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2009.12.003"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.2001.924670"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2008.31"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5929024\/05484445.pdf?arnumber=5484445","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:13Z","timestamp":1633913053000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5484445\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,7]]},"references-count":22,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2050158","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,7]]}}}